Abstract: A microprocessor avoids loss of instructions in a pre-fetch procedure when a branch instruction is received. When a new branch instruction that specifies a branch end is received by a queue buffer, all the instructions preceding the specified branch end are processed as an operand of the branch instruction. Moreover, the instruction word length of the branch instruction including the instruction that has been processed as the operand is output to a program counter, so the queue buffer is not flushed.

Abstract: An operation control signal for an oscillator producing an internal clock signal phase-locked with a basic clock signal is applied to a second internal clock generating circuit. In the second internal clock generating circuit, with reference to the applied operation control signal, a control signal adjusting a phase and/or frequency difference between a synchronization target signal and a second internal clock signal is produced to adjust a phase and/or frequency of the second internal clock signal. A plurality of internal clock signals different in phase and/or frequency can be generated accurately and stably.

Abstract: A receiver of a communication device includes: a differential amplification circuit; two capacitors for applying only the amplitude components of two input clock signals complementary to each other to the gates of two N-channel MOS transistors of the differential amplification circuit; and an initialization circuit for applying a predetermined reference potential to the gates of the two N-channel MOS transistors in a non data communication state. Thus, it is possible to make a quick and stable transition from a non data communication state to a data communication state.

Abstract: N-bit external data input from the outside is converted to m-bit data (m>n) by simultaneous write circuits and the m-bit data is supplied to a semiconductor memory. When m-bit data is read out of the semiconductor memory, coincidence judgement results are output. Thus, in a memory-logic-combined integrated circuit, the semiconductor memory can be efficiently tested without a lot of external data input/output terminals.

Abstract: An operation control signal for an oscillator producing an internal clock signal phase-locked with a basic clock signal is applied to a second internal clock generating circuit. In the second internal clock generating circuit, with reference to the applied operation control signal, a control signal adjusting a phase and/or frequency difference between a synchronization target signal and a second internal clock signal is produced to adjust a phase and/or frequency of the second internal clock signal. A plurality of internal clock signals different in phase and/or frequency can be generated accurately and stably.

Abstract: A plurality of patterned lead wires equally spaced are arranged on both side ends of a lead substrate, a plurality of pads equally spaced are arranged on both side ends of a semiconductor chip, and the semiconductor chip is mounted on the lead substrate so as to connect the pads of each side end of the semiconductor chip with the patterned lead wires of the corresponding side end of the lead substrate. Widths of the patterned lead wires are smaller than a width of an open space between each pair of pads adjacent to each other in the semiconductor chip, and widths of the pads of the semiconductor chip are larger than a width of an open space between each pair of patterned lead wires adjacent to each other.

Abstract: A new branch instruction that specifies a branch end is added. When this branch instruction is received, all the instructions preceding the specified branch end are processed as an operand of the branch instruction. Moreover, the instruction word length of the branch instruction including the instruction that has been processed as the operand is output to the program counter, and the queue buffer is not flushed.

Abstract: N-bit external data input from the outside is converted to m-bit data (m>n) by simultaneous write circuits and the m-bit data is supplied to a semiconductor memory. When m-bit data is read out of the semiconductor memory, coincidence judgement results are output. Thus, in a memory-logic-combined integrated circuit, the semiconductor memory can be efficiently tested without a lot of external data input/output terminals.

Abstract: A replacement IO program circuit is provided for each of memory blocks coupled commonly to a data bus of multiple bits, and a replacement column address program circuit is provided for a predetermined number of memory blocks. The state of use of a redundant column can be independently determined in each memory block, and the number of program circuits and the area occupied by the circuits are reduced. A semiconductor memory device includes a defective column repairing circuit allowing efficient use of the redundant column without increasing a chip area.

Abstract: A static type semiconductor memory device includes a main bit line pair, and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair, a static memory connected to the local bit line pair, an amplifier which amplifies potential difference between the paired local bit lines, and a data transfer gate which transfers data between the local bit line pair and the main bit line pair.

Abstract: An SRAM includes a memory cell array, a peripheral circuitry including a bit line load connected to the memory cell array, a multiplexer and the like, and a voltage lowering circuit. The voltage lowering circuit receives a power supply potential Vcc and outputs a potential Vin which is lower. The potential Vin is applied to the peripheral circuitry except the memory cell array, and the power supply potential Vcc is directly applied to the memory cell array. Therefore, operational potential of the memory cell array is made relatively higher with respect to the peripheral circuitry. As a result, a static semiconductor memory device which can operation at low voltage and consumes less power can be provided.

Abstract: A static RAM includes: a memory cell array including word lines, bit line pairs and memory cells; a row recorder; a column decoder; a DTD signal generator responsive to transition of input data or transition of a write enable signal for generating a data transition detection signal for a prescribed time period; and a write driver responsive to the write enable signal and the data transition detection signal for supplying the input data to a bit line pair selected by the column decoder. Even when there is a noise in write enable signal during reading cycle and data transition detection signal is generated erroneously, erroneous writing of data can be prevented, since write enable signal is not supplied to the write driver.

Abstract: One transmission gate and one fuse are provided in series corresponding to a predecode signal. A fuse for turning on or off the transmission gate and a fuse for grounding an output are provided. When a redundancy memory cell row is not used, all the fuses are connected. The transmission gate is turned off, and the output is grounded. When the redundancy memory cell row is used, all the fuses excluding one fuse corresponding to the predecode signal to be transmitted are disconnected.

Abstract: An improved SRAM is disclosed including a plurality of memory blocks each having a redundancy memory cell to be shared. In redundancy row decoders 50a, 50b, 50c provided in each memory block, a memory block to be remedied is programmed. Accordingly, a redundancy memory cell row corresponding to each redundancy row decoder can be used for remedy of a defect memory cell in another memory block. Since a defect memory cell may be remedied flexibly, the yield rate in production of semiconductor memories is improved.

Abstract: A semiconductor memory device having a circuit for preventing the operation of a test mode includes a first terminal for receiving an externally applied high voltage exceeding a power supply potential, a second terminal for receiving an externally applied test mode signal and a high voltage detector for detecting that a high voltage signal has been applied through the first terminal. A test mode signal holding circuit is responsive to the high voltage detector and holds the test mode signal applied through the second terminal. A test circuit is responsive to the test mode signal held in the test mode signal holding circuit and performs a test in the semiconductor memory device. A disabling circuit is provided to disable the high voltage detector.

Abstract: When a pre-shipment test of a SRAM is requested, a pulse signal PL having a pulse width exceeding a predetermined time length is applied through a terminal 62. A pulse width detecting circuit 80 detects the pulse width of the applied pulse signal to provide a holding signal HD. A test mode signal holding circuit 90 holds an externally applied test mode request signal TM' in response to the holding signal HD. After the completion of the pre-shipment test, pulse width detecting circuit 80 is disabled by a fusion of a fuse 71. Fuse 71 is fused after the pre-shipment test is conducted, whereby the test mode operation is prevented from undesirably occurring.