Patents by Inventor Yoshiyuki Hiroshima

Yoshiyuki Hiroshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10877216
    Abstract: An optical waveguide substrate includes a substrate that includes a recess, a buffer layer disposed on a bottom surface and a wall surface of the recess, and an optical waveguide disposed inside the recess with the buffer layer interposed therebetween and having a cladding layer disposed on the buffer layer and a core layer disposed inside the cladding layer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: December 29, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kohei Choraku, Akiko Matsui, Yoshiyuki Hiroshima, Kazuki Takahashi, Tetsuro Yamada
  • Publication number: 20200303849
    Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, YOSHIYUKI HIROSHIMA, Kohei Choraku, Kazuki TAKAHASHI, AKIKO MATSUI, Shigeo Iriguchi
  • Patent number: 10783309
    Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, ??={(L×?×?t×E)/(D×T)}×m×?×?×?; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Akiko Matsui, Naoki Nakamura
  • Patent number: 10714849
    Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, Yoshiyuki Hiroshima, Kohei Choraku, Kazuki Takahashi, Akiko Matsui, Shigeo Iriguchi
  • Publication number: 20200026816
    Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, ??={(L×?×?t×E)/(D×T)}×m×?×?×?; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 23, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Mitsunori Abe, YOSHIYUKI HIROSHIMA, Takahiro KITAGAWA, AKIKO MATSUI, Naoki Nakamura
  • Patent number: 10492291
    Abstract: A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: November 26, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiyuki Hiroshima, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Publication number: 20190324207
    Abstract: An optical waveguide substrate includes a substrate that includes a recess, a buffer layer disposed on a bottom surface and a wall surface of the recess, and an optical waveguide disposed inside the recess with the buffer layer interposed therebetween and having a cladding layer disposed on the buffer layer and a core layer disposed inside the cladding layer.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Kohei Choraku, AKIKO MATSUI, YOSHIYUKI HIROSHIMA, Kazuki TAKAHASHI, Tetsuro Yamada
  • Publication number: 20190245284
    Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 8, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, YOSHIYUKI HIROSHIMA, Kohei Choraku, Kazuki TAKAHASHI, AKIKO MATSUI, Shigeo Iriguchi
  • Publication number: 20190220564
    Abstract: A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, ??={(L×?×?t×E)/(D×T)}×m, where ?? is the amount of distortion, L is a length of the via, ? is a thermal expansion coefficient of a base material, ?t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n×365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression Nx=C/??.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 18, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Mitsunori ABE, YOSHIYUKI HIROSHIMA, Takahiro KITAGAWA, Naoki NAKAMURA, AKIKO MATSUI
  • Patent number: 10353158
    Abstract: A light emitting element bonded board includes an optical waveguide formed within a board, a hollowed portion in the board, a light emitting element installed in the hollowed portion, and a conductive portion formed in an upper layer and/or a lower layer of the optical waveguide, wherein an optical axis of the light emitting element coincides with a center line of the optical waveguide, and a bonding portion of the light emitting element is bonded to the conductive portion.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 16, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiyuki Hiroshima, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Patent number: 10212805
    Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: February 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Yamada, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Yoshiyuki Hiroshima, Kohei Choraku
  • Patent number: 10164312
    Abstract: A wiring board includes: a first substrate that includes signal wiring; a second substrate that includes a conductor with an area larger than an area of the signal wiring, and projection formed on a face of the conductor and constituted of an insulator with a pattern corresponding to a pattern of the signal wiring, the second substrate being arranged so that the face of the conductor on which the projection is formed faces the signal wiring; and an intermediate layer that is arranged between the signal wiring and the conductor and includes a fibrous member.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 25, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Yamada, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Yoshiyuki Hiroshima, Kohei Choraku
  • Patent number: 10151878
    Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 11, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Kohei Choraku, Akiko Matsui, Tetsuro Yamada, Yoshiyuki Hiroshima
  • Publication number: 20180184514
    Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.
    Type: Application
    Filed: November 9, 2017
    Publication date: June 28, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Yamada, AKIKO MATSUI, Mitsuhiko Sugane, Takahide Mukoyama, YOSHIYUKI HIROSHIMA, Kohei Choraku
  • Publication number: 20180156993
    Abstract: A light emitting element bonded board includes an optical waveguide formed within a board, a hollowed portion in the board, a light emitting element installed in the hollowed portion, and a conductive portion formed in an upper layer and/or a lower layer of the optical waveguide, wherein an optical axis of the light emitting element coincides with a center line of the optical waveguide, and a bonding portion of the light emitting element is bonded to the conductive portion.
    Type: Application
    Filed: November 15, 2017
    Publication date: June 7, 2018
    Applicant: FUJITSU LIMITED
    Inventors: YOSHIYUKI HIROSHIMA, AKIKO MATSUI, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Patent number: 9992878
    Abstract: A circuit board disclosed herein includes: two substrates opposed to each other, where a dielectric being interposed between the two substrates; a through hole formed in each of the two substrates and filled with the dielectric; a first conductor film formed on an inner surface of the through hole; and a second conductor film covering the through hole on a main surface of each of the two substrates on an opposite side to the dielectric, the second conductor film being connected to the first conductor film on the main surface side.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: June 5, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Mitsuhiko Sugane, Akiko Matsui, Takahide Mukoyama, Tetsuro Yamada, Yoshiyuki Hiroshima, Kohei Choraku
  • Publication number: 20170293095
    Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 12, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kohei Choraku, AKIKO MATSUI, Tetsuro Yamada, YOSHIYUKI HIROSHIMA
  • Publication number: 20170290144
    Abstract: A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.
    Type: Application
    Filed: March 22, 2017
    Publication date: October 5, 2017
    Applicant: FUJITSU LIMITED
    Inventors: YOSHIYUKI HIROSHIMA, AKIKO MATSUI, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Patent number: 9763331
    Abstract: A printed circuit board includes: a first electrode made of a tubular electric conductor formed on an inner wall of a first hole formed in the printed circuit board; a dielectric body disposed inside the first electrode; and a second electrode made of a tubular electric conductor formed on an inner wall of a second hole extending through the dielectric body, the second electrode having a center axis concentric with the first electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiyuki Hiroshima, Naoki Nakamura, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Patent number: 9715062
    Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kohei Choraku, Akiko Matsui, Tetsuro Yamada, Yoshiyuki Hiroshima