Abstract: A wiring topology display method, includes: obtaining layout information indicating positions of components and wiring coupling the components; dividing first wiring into first pieces of partial wiring, and generating partial wiring information indicating the first pieces of partial wiring; identifying a first length of the partial wiring and a first angle of the partial wiring for a vector; identifying combinations of second pieces of partial wiring based on the first length and the first angle, the second pieces of partial wiring having second lengths which are a certain length or more, second angles which are different by a certain angle, and a distance which is a certain distance or less; identifying a group having the combinations including pieces of identical partial wiring; and symbolizing third pieces of partial wiring at both ends of the group and fourth pieces of partial wiring between the third pieces of partial wiring.

Abstract: A computer-readable-recording-medium stored a program for causing a computer to execute: judging, for each of elements of a plurality of scattering parameters, whether a difference between a first-area in a plane containing an axis representing frequency and an axis representing the element, and a second-area in the plane is within a permissible range, the first-area being surrounded by a first-element-value series of the element that is defined in advance for a plurality of first-frequencies, the second-area being surrounded by a second-element-value series that is obtained by performing interpolation calculation from the first-element-value series for a plurality of second frequencies which are different from the plurality of first-frequencies and which are provided at regular intervals; and determining, by performing the judging for one interval or a plurality of intervals, an interval so that the difference falls within the permissible range for all of the elements of the plurality of scattering parameter

Abstract: A wiring topology display method, includes: obtaining layout information indicating positions of components and wiring coupling the components; dividing first wiring into first pieces of partial wiring, and generating partial wiring information indicating the first pieces of partial wiring; identifying a first length of the partial wiring and a first angle of the partial wiring for a vector; identifying combinations of second pieces of partial wiring based on the first length and the first angle, the second pieces of partial wiring having second lengths which are a certain length or more, second angles which are different by a certain angle, and a distance which is a certain distance or less; identifying a group having the combinations including pieces of identical partial wiring; and symbolizing third pieces of partial wiring at both ends of the group and fourth pieces of partial wiring between the third pieces of partial wiring.

Abstract: A computer-readable-recording-medium stored a program for causing a computer to execute: judging, for each of elements of a plurality of scattering parameters, whether a difference between a first-area in a plane containing an axis representing frequency and an axis representing the element, and a second-area in the plane is within a permissible range, the first-area being surrounded by a first-element-value series of the element that is defined in advance for a plurality of first-frequencies, the second-area being surrounded by a second-element-value series that is obtained by performing interpolation calculation from the first-element-value series for a plurality of second frequencies which are different from the plurality of first-frequencies and which are provided at regular intervals; and determining, by performing the judging for one interval or a plurality of intervals, an interval so that the difference falls within the permissible range for all of the elements of the plurality of scattering parameter

Abstract: An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.

Abstract: An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.

Abstract: In order to achieve augmentation of the accuracy in calculation of noise and augmentation of the accuracy in a noise check which is performed, for example, when an electronic circuit is designed and further realize significant reduction of the time required for a noise check and augmentation of the operation efficiency by reduction of the man-hours of a designer in a noise analysis, a noise checking apparatus includes a model production section (3) for producing a simulation model of a circuit portion relating to a noticed wiring line, a simulation section (4) for performing a simulation using the simulation model to calculate a signal waveform which propagates in the noticed wiring line and calculate a noise waveform superposed on the signal waveform for each kind of noise, a noise waveform synthesis section (5) for synthesizing the signal waveform and the noise waveforms with generation timings of the noise waveforms taken into consideration to obtain a noise composite waveform, and a noise checking section

Abstract: A power supply noise analysis model generator models power supply layers in circuit boards, and includes: a CAD data obtaining section that obtains CAD data; a CAD data conversion section that converts CAD data into data suitable for noise analysis; a power supply pair extraction section that extracts a power supply pair; a mesh division section that divides a power supply pair region into meshes; a ripple processing section that arranges ripples as wave fronts of electromagnetic waves radiated into the power supply pair region from elements thereon; a node layout section that positions plural nodes on the power supply pair region; a node region determination section that determines node regions; an LRC determination section that determines L, R and C connecting the nodes; a power supply layer model generation section that generates a power supply layer model; and a power supply noise analysis model generation section that generates a power supply noise analysis model.

Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.

Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.

Abstract: Disclosed is an interactive CAD apparatus for logic circuit packaging design, wherein provisions are made to display delay times in real time when a component is being moved, so that error-contributing components and interconnections can be easily identified and the optimum position can be easily determined.

Abstract: A load sharing method for a parallel computer system having a computer group including a plurality of computers and an operation management mechanism which is a computer for managing the operation of the computer group.

Abstract: The logic equipment delay time analysis system provides not only a number of parallel dedicated delay time processors which perform calculation of the delay time, but also a processor-to-processor communications device which is connected to each of the delay time processors and performs communications between these delay time processors. The circuit model of the logic equipment is divided by a circuit model division section into a number of small logic circuits, Data with regard to each of the divided circuit models is assigned to the individual delay time processors and initial values are set into each of the delay time processors, so that the delay times for all paths from each pin at which a signal is input to circuits at which output signals are generated are calculated.