Patents by Inventor Yoshiyuki Kawana

Yoshiyuki Kawana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8067296
    Abstract: The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm2 to 1 MW/cm2 for a short time of 0.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: November 29, 2011
    Assignees: Success International Corporation, Hightec Systems Corporation
    Inventors: Yoshiyuki Kawana, Naoki Sano
  • Publication number: 20100190296
    Abstract: The present invention provides a method of manufacturing a semiconductor device in which a thinned substrate of a semiconductor or semiconductor device is handled without cracks in the substrate and treated with heat to improve a contact between semiconductor back surface and metal in a high yield and a semiconductor device may be manufactured in a high yield. In the method of manufacturing a semiconductor device according to the present invention, a notched part is formed from a surface to a middle in a semiconductor substrate by dicing and the surface of the substrate is fixed to a support base. Next, a back surface of the substrate is ground to thin the semiconductor substrate and then a metal electrode and a carbon film that is a heat receiving layer are sequentially formed on the back surface of the substrate. Next, the carbon film is irradiated with light at a power density of 1 kW/cm2 to 1 MW/cm2 for a short time of 0.
    Type: Application
    Filed: November 8, 2006
    Publication date: July 29, 2010
    Applicants: Success International Corporation, Hightec Systems Corporation
    Inventors: Yoshiyuki Kawana, Naoki Sano
  • Patent number: 7435668
    Abstract: A solution containing impurity ions is applied onto the surface of a silicon film to form a solution layer, followed by drying into a compound layer containing the impurities. Heat treatment is performed by irradiation with an energy beam so as to diffuse the impurity atoms in the compound layer toward the silicon film into a source region and a drain region. Subsequently, the compound layer is removed.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: October 14, 2008
    Assignee: Sony Corporation
    Inventors: Akio Machida, Takahiro Kamei, Yoshiyuki Kawana
  • Publication number: 20050181566
    Abstract: A solution containing impurity ions is applied onto the surface of a silicon film to form a solution layer, followed by drying into a compound layer containing the impurities. Heat treatment is performed by irradiation with an energy beam so as to diffuse the impurity atoms in the compound layer toward the silicon film into a source region and a drain region. Subsequently, the compound layer is removed.
    Type: Application
    Filed: January 24, 2005
    Publication date: August 18, 2005
    Applicant: Sony Corporation
    Inventors: Akio Machida, Takahiro Kamei, Yoshiyuki Kawana
  • Patent number: 4176372
    Abstract: A polycrystalline layer is formed as a passivation layer on a monocrystalline semiconductor substrate, the polycrystalline layer containing oxygen in the range between 2 to 45 atomic percent. The density of surface states between the surface of said substrate and the polycrystalline silicon layer is less than 10.sup.10 /cm.sup.2 .multidot.eV at the middle portion of a forbidden band, and the interface density of fixed charge in the polycrystalline layer is less than 10.sup.10 /cm.sup.2.
    Type: Grant
    Filed: December 5, 1977
    Date of Patent: November 27, 1979
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Hisao Hayashi, Teruaki Aoki, Hisayoshi Yamoto, Yoshiyuki Kawana
  • Patent number: 3977019
    Abstract: A semiconductor integrated circuit, in which an isolation region with one conductivity type and a plurality of island regions with another conductivity type separated by the isolation region are provided, is disclosed. In this case, a high resistance polycrystalline semiconductor layer is formed to cover whole of a surface portion of a PN-junction formed between the isolation region and the island regions.
    Type: Grant
    Filed: May 14, 1974
    Date of Patent: August 24, 1976
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Yoshiyuki Kawana
  • Patent number: 3971061
    Abstract: A semiconductor device is provided having at least two semiconductor regions of opposite conductivity type and forming a planar-type PN junction. A field limiting ring is disposed spaced from the PN junction. A high-resistivity polycrystalline silicon layer covers the PN junction and the field limiting ring.
    Type: Grant
    Filed: May 15, 1974
    Date of Patent: July 20, 1976
    Assignee: Sony Corporation
    Inventors: Takeshi Matsushita, Hisao Hayashi, Yoshiyuki Kawana