Patents by Inventor Yoshiyuki Kawazu

Yoshiyuki Kawazu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7741674
    Abstract: An object is to improve a data recording amount per memory cell. In the invention, in a non-volatile memory, the data contents of which can be electrically written and erased, each memory cell that configures the non-volatile memory is provided with: source/drain regions formed on a semiconductor substrate; a gate electrode formed on a channel region of the semiconductor substrate; and a gate insulating film formed between the semiconductor substrate and the gate electrode. A configuration in which the source/drain regions extend at least in three directions from the channel region when seen on a plane from the gate electrode side is employed.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 22, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshiyuki Kawazu
  • Patent number: 7349248
    Abstract: A non-volatile memory cell includes an upper electrode; a lower electrode and a state-variable region, in which a conductive state changes only once. The state variable region is formed in a region between the upper electrode and the lower electrode. The state-variable region comprises a first semiconductor layer of a first conductive type; and second semiconductor layers of a second conductive type, opposing to the first conductive type, which are formed on upper and lower surfaces of the first semiconductor layer via PN junctions.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: March 25, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshiyuki Kawazu, Hiroyuki Tanaka
  • Publication number: 20080017919
    Abstract: An object is to improve a data recording amount per memory cell. In the invention, in a non-volatile memory, the data contents of which can be electrically written and erased, each memory cell that configures the non-volatile memory is provided with: source/drain regions formed on a semiconductor substrate; a gate electrode formed on a channel region of the semiconductor substrate; and a gate insulating film formed between the semiconductor substrate and the gate electrode. A configuration in which the source/drain regions extend at least in three directions from the channel region when seen on a plane from the gate electrode side is employed.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 24, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Yoshiyuki Kawazu
  • Publication number: 20070258285
    Abstract: A non-volatile memory cell includes an upper electrode; a lower electrode and a state-variable region, in which a conductive state changes only once. The state variable region is formed in a region between the upper electrode and the lower electrode. The state-variable region comprises a first semiconductor layer of a first conductive type; and second semiconductor layers of a second conductive type, opposing to the first conductive type, which are formed on upper and lower surfaces of the first semiconductor layer via PN junctions.
    Type: Application
    Filed: January 24, 2007
    Publication date: November 8, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventors: Yoshiyuki Kawazu, Hiroyuki Tanaka
  • Patent number: 5966602
    Abstract: A method of fabricating a nonvolatile semiconductor memory includes an oxide area forming step, a word line forming step, an etching step and a source area forming step in turn. In the oxide area forming step, oxide areas are formed in parallel bands. In the word line forming step, word lines are formed in parallel and perpendicularly to the oxide bands formed in the oxide area forming step. In the etching step, oxides, existing in areas between pairs of adjacent word lines in which source regions are to be formed, are etched, whereby field areas are created from the oxide areas. And in the source area forming step, areas functioning as source regions and source lines are formed between the word line pairs by doping impurity into the semiconductor substrate.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: October 12, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshiyuki Kawazu, Susumu Miyagi
  • Patent number: 5920122
    Abstract: A titanium film is formed in a contact hole defined in a silicon substrate. The titanium film is transformed into a titanium silicide film and a first titanium nitride film by high-temperature lamp anneal. Further, a second titanium nitride film is stacked on the first titanium nitride film. Conditions are applied under which the titanium nitride films are formed into a granular crystal of primarily a (200) orientation. Therefore, barrier characteristics of the titanium nitride films to silicon atoms is not compromised even in the case of a subsequent high-temperature thermal treatment.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: July 6, 1999
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Ryoichi Matsumoto, Yoshiyuki Kawazu
  • Patent number: 5654235
    Abstract: A titanium film is formed in a contact hole defined in a silicon substrate. The titanium film is transformed into a titanium silicide film and a first titanium nitride film by high-temperature lamp anneal. Further, a second titanium nitride film is stacked on the first titanium nitride film. Conditions are applied under which the titanium nitride films are formed into a granular crystal of primarily a (200) orientation. Therefore, barrier characteristics of the titanium nitride films to silicon atoms is not compromised even in the case of a subsequent high-temperature thermal treatment.
    Type: Grant
    Filed: June 22, 1995
    Date of Patent: August 5, 1997
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Ryoichi Matsumoto, Yoshiyuki Kawazu
  • Patent number: 5324600
    Abstract: In a photomask for use in forming a resist pattern by projection exposure of a resist through the photomask, a phase shifter has a first edge part whose image is to be transferred and a second edge part whose image is not to be transferred. A light attenuator is provided to cover the first edge part. The light attenuator may include an array of opaque stripes arranged at a pitch of not more than the limit of resolution, i.e., 0.5.times..lambda./NA, where .lambda. represents the wavelength of light used for the projection exposure, and NA represents the numerical aperture of an optical system used for the projection exposure. In another embodiment, the light attenuator is formed to cover a shifter edge part in alignment with a line of a transmission mask. In a further embodiment, one or more light attenuators having different transparency are used to obtain lines of a resist pattern having different widths.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: June 28, 1994
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hideyuki Jinbo, Yoshiyuki Kawazu, Yoshio Yamashita