Patents by Inventor Yoshiyuki Miyayama
Yoshiyuki Miyayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6959375Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: GrantFiled: October 29, 2002Date of Patent: October 25, 2005Assignee: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6954847Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.Type: GrantFiled: February 4, 2002Date of Patent: October 11, 2005Assignee: Transmeta CorporationInventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
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Patent number: 6948052Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: GrantFiled: October 29, 2002Date of Patent: September 20, 2005Assignee: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6941447Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: GrantFiled: November 5, 2003Date of Patent: September 6, 2005Assignee: Seiko Epson CorporationInventors: Le-Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6934829Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: GrantFiled: October 31, 2003Date of Patent: August 23, 2005Assignee: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6922795Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].Type: GrantFiled: November 5, 2003Date of Patent: July 26, 2005Assignee: Seiko Epson CorporationInventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
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Patent number: 6915412Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: GrantFiled: October 30, 2002Date of Patent: July 5, 2005Assignee: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Publication number: 20050102579Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].Type: ApplicationFiled: November 12, 2004Publication date: May 12, 2005Applicant: Seiko Epson CorporationInventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
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Patent number: 6799157Abstract: An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation mode, the access of CPU to an internal ROM is switched to the access of CPU to the emulation memory through an external bus. The emulation mode is turned ON or OFF through a mode selection terminal or mode selection register. The emulation memory is controlled by a control signal CNT2 different from a control signal CNT1 which controls the external memory. A memory read signal in CNT2 become active at a timing earlier than that of a memory read signal in CNT1. Thus, the instruction is fetched and decoded within one clock cycle. A mode selection terminal is further provided for selecting a mode of performing the boot from the emulation memory, internal ROM or external memory and a made of selecting OPT mode.Type: GrantFiled: March 21, 2000Date of Patent: September 28, 2004Assignee: Seiko Epson CorporationInventors: Makoto Kudo, Hirofumi Terasawa, Yoshiyuki Miyayama
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Publication number: 20040153812Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer.Type: ApplicationFiled: November 5, 2003Publication date: August 5, 2004Applicant: Seiko Epson CorporationInventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
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Publication number: 20040128487Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.Type: ApplicationFiled: November 17, 2003Publication date: July 1, 2004Applicant: Seiko Epson CorporationInventors: Cheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Publication number: 20040093482Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: ApplicationFiled: November 5, 2003Publication date: May 13, 2004Applicant: Seiko Epson CorporationInventors: Le-Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Publication number: 20040093485Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: ApplicationFiled: November 5, 2003Publication date: May 13, 2004Applicant: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Publication number: 20040093483Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: ApplicationFiled: October 31, 2003Publication date: May 13, 2004Applicant: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Publication number: 20040054872Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: ApplicationFiled: September 12, 2003Publication date: March 18, 2004Applicant: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6665821Abstract: The present invention provides a microcomputer that makes, it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].Type: GrantFiled: February 4, 2000Date of Patent: December 16, 2003Assignee: Seiko Epson CorporationInventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
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Patent number: 6647485Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: GrantFiled: May 10, 2001Date of Patent: November 11, 2003Assignee: Seiko Epson CorporationInventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
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Patent number: 6560692Abstract: The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient description of processes that save and restore the contents of registers, increasing the speed of processing of interrupts and subroutine calls and returns. A CPU that uses this data processing circuit comprises a dedicated stack pointer register SP and uses an instruction decoder to decode a group of dedicated stack pointer instructions that specify the SP as an implicit operand. This group of dedicated stack pointer instructions are implemented in hardware by using general-purpose registers, the PC, the SP, an address adder, an ALU, a PC incrementer, internal buses, internal signal lines, and external buses.Type: GrantFiled: May 20, 1997Date of Patent: May 6, 2003Assignee: Seiko Epson CorporationInventors: Makoto Kudo, Satoshi Kubota, Yoshiyuki Miyayama, Hisao Sato
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Publication number: 20030084270Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.Type: ApplicationFiled: February 4, 2002Publication date: May 1, 2003Applicant: Transmeta Corp.Inventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
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Publication number: 20030079113Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.Type: ApplicationFiled: October 29, 2002Publication date: April 24, 2003Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang