Patents by Inventor Yoshiyuki MOTOBA

Yoshiyuki MOTOBA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9509992
    Abstract: An image compression/decompression device achieving increased utilization efficiency of the memory bandwidth in the access to the memory used for the compression/decompression operation while maintaining ill effect on the images at a low level is realized. The image compression/decompression device comprises a data conversion unit which reduces the data access rate when original images (as input images at the time of performing the compression) and reference images (used for performing the interframe prediction) are stored in the memory by accessing the memory. The access to the memory is performed in an address sequence (order) that differs between data write and data read. This makes it possible to increase the utilization efficiency of the memory bandwidth, and further to reduce the capacity of the buffer memory used for the data read.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 29, 2016
    Assignee: HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.
    Inventors: Hironori Komi, Yusuke Yatabe, Kyohei Unno, Yoshiyuki Motoba, Toshiaki Hori, Yoshimasa Kashihara, Toshikazu Yanagihara
  • Publication number: 20140177710
    Abstract: An image compression/decompression device achieving increased utilization efficiency of the memory bandwidth in the access to the memory used for the compression/decompression operation while maintaining ill effect on the images at a low level is realized. The image compression/decompression device comprises a data conversion unit which reduces the data access rate when original images (as input images at the time of performing the compression) and reference images (used for performing the interframe prediction) are stored in the memory by accessing the memory. The access to the memory is performed in an address sequence (order) that differs between data write and data read. This makes it possible to increase the utilization efficiency of the memory bandwidth, and further to reduce the capacity of the buffer memory used for the data read.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 26, 2014
    Applicant: HITACHI INFORMATION & TELECOMMUNICATION ENGINEERING, LTD.
    Inventors: Hironori KOMI, Yusuke YATABE, Kyohei UNNO, Yoshiyuki MOTOBA, Toshiaki HORI, Yoshimasa KASHIHARA, Toshikazu YANAGIHARA