Abstract: A plurality of semiconductor devices provided on a silicon carbide substrate are provided with electrode layers, respectively. The silicon carbide substrate is cut at a region of an exposed surface of the silicon carbide substrate that separates the electrode layers to individually separate the semiconductor devices. A stress relaxation resin is applied to each individually separated semiconductor device to cover the exposed surface at a peripheral end portion of that surface of the semiconductor device which has the electrode layer thereon. A semiconductor apparatus can thus be obtained that also allows a semiconductor device with a silicon carbide or similar compound semiconductor substrate to adhere to a sealant resin via large adhesive strength and thus allows the sealant resin to be less crackable, less peelable and the like by thermal stress caused in operation.

Abstract: A plurality of semiconductor elements for power control are formed on a semiconductor substrate. A stress relaxation resin layer covering a crossing region where band-shaped dicing areas dividing the semiconductor elements adjacent to each other cross is formed. The crossing region is diced to cut the stress relaxation resin layer to obtain the separate semiconductor elements. Accordingly, even with semiconductor elements produced with a compound semiconductor substrate of SiC or the like, a semiconductor device having high adhesive strength with a sealing resin and being less likely to cause cracking or peeling of the sealing resin due to thermal stress during an operation can be obtained.

Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.

Abstract: A plurality of semiconductor devices provided on a silicon carbide substrate are provided with electrode layers, respectively. The silicon carbide substrate is cut at a region of an exposed surface of the silicon carbide substrate that separates the electrode layers to individually separate the semiconductor devices. A stress relaxation resin is applied to each individually separated semiconductor device to cover the exposed surface at a peripheral end portion of that surface of the semiconductor device which has the electrode layer thereon. A semiconductor apparatus can thus be obtained that also allows a semiconductor device with a silicon carbide or similar compound semiconductor substrate to adhere to a sealant resin via large adhesive strength and thus allows the sealant resin to be less crackable, less peelable and the like by thermal stress caused in operation.

Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

Abstract: A plurality of semiconductor elements for power control are formed on a semiconductor substrate. A stress relaxation resin layer covering a crossing region where band-shaped dicing areas dividing the semiconductor elements adjacent to each other cross is formed. The crossing region is diced to cut the stress relaxation resin layer to obtain the separate semiconductor elements. Accordingly, even with semiconductor elements produced with a compound semiconductor substrate of SiC or the like, a semiconductor device having high adhesive strength with a sealing resin and being less likely to cause cracking or peeling of the sealing resin due to thermal stress during an operation can be obtained.

Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.

Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.

Abstract: A RESURF layer including a plurality of P-type implantation layers having a low concentration of P-type impurity is formed adjacent to an active region. The RESURF layer includes a first RESURF layer, a second RESURF layer, a third RESURF layer, a fourth RESURF layer, and a fifth RESURF layer that are arranged sequentially from the P-type base side so as to surround the P-type base. The second RESURF layer is configured with small regions having an implantation amount equal to that of the first RESURF layer and small regions having an implantation amount equal to that of the third RESURF layer being alternately arranged in multiple. The fourth RESURF layer is configured with small regions having an implantation amount equal to that of the third RESURF layer and small regions having an implantation amount equal to that of the fifth RESURF layer being alternately arranged in multiple.

Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.

Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.

Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. A RESURF layer (101) including a plurality of P-type implantation layers having a relatively low concentration of P-type impurity is formed adjacent to an active region (2). The RESURF layer (101) includes a first RESURF layer (11), a second RESURF layer (12), a third RESURF layer (13), a fourth RESURF layer (14), and a fifth RESURF layer (15) that are arranged sequentially from the P-type base (2) side so as to surround the P-type base (2). The second RESURF layer (12) is configured with small regions (11?) having an implantation amount equal to that of the first RESURF layer (11) and small regions (13?) having an implantation amount equal to that of the third RESURF layer (13) being alternately arranged in multiple.

Abstract: A thermal-type infrared image sensing device and method of producing a thermal-type infrared image sensing device are provided. The thermal-type infrared image sensing device includes pixel elements that are two-dimensionally arranged on a semiconductor substrate. Each pixel element includes a detector that detects temperature, an infrared-light absorber that absorbs incident infrared light and that converts the light into heat, and a support that supports the detector apart from the semiconductor substrate. The thermal-type infrared image sensing device also includes reference-pixel elements that are arranged adjacent to and along a row of the pixel elements. Each of the reference pixels generates a reference signal, and each of the reference pixels includes a structure that shields a detector from incident infrared light. The detectors of the pixel elements and the reference-pixel elements are each connected to the semiconductor substrate through the respective supports.

Abstract: An infrared image sensing device is provided having a pixel structure in which an output level as a reference voltage of a reference-pixel element is close to that of a pixel element.

Abstract: A thermal infrared sensor device includes a substrate having a concave portion, a temperature detecting portion connected to the substrate via a supporting leg held at an upper portion of a space within the concave portion, an infrared reflecting film covering at least a portion of the supporting leg without being thermally connected to the temperature detecting portion, and an absorbing hood portion held opposite the infrared reflecting film and thermally connected to the temperature detecting portion, without being thermally connected to the infrared reflecting film, and extending laterally, in a plate shape, covering at least a portion of the infrared reflecting film.

Abstract: A thermal infrared sensor device includes a substrate having a concave portion, a temperature detecting portion connected to the substrate via a supporting leg held at an upper portion of a space within the concave portion, an infrared reflecting film covering at least a portion of the supporting leg without being thermally connected to the temperature detecting portion, and an absorbing hood portion held opposite the infrared reflecting film and thermally connected to the temperature detecting portion, without being thermally connected to the infrared reflecting film, and extending laterally, in a plate shape, covering at least a portion of the infrared reflecting film.

Abstract: A method of manufacturing an infrared image sensor in which an etching gas is introduced through etching holes into a semiconductor substrate to form a hollow portion. The etching gas is introduced only through an etching hole in a splicing pillar when etching is started. This method provides an etching configuration which has a largest depth right beneath the splicing pillar and which becomes shallower toward ends of the substrate, and therefore there is no need for forming deep etching stoppers.

Abstract: An infrared detector includes an optical cavity structure with an infrared reflection film on a semiconductor substrate. The infrared reflection film and an infrared absorption film provide high efficiency infrared detection.

Abstract: Present invention provides a method of manufacturing an infrared image sensor in which an etching gas is introduced through etching holes in a plurality of positions into a semiconductor substrate to form a hollow portion, the etching gas is introduced only through an etching hole in a splicing pillar when etching is started. This method makes it possible to obtain this provides an etching configuration which has a largest depth right beneath the splicing pillar and which becomes shallower toward ends of the substrate, and therefore there is no need for forming deep etching stoppers as in the prior art.

Abstract: A sensor element provided with a silicon substrate having a semiconductor circuit, a sensing-element portion formed on the silicon substrate and connected to the semiconductor circuit, and a cavity portion formed by removing a silicon substrate portion below the sensing-element portion, in which a removal resistance region having resistance against substrate removal is provided in the silicon substrate between the semiconductor circuit and the cavity portion.