Patents by Inventor Yoshiyuki Nasuno

Yoshiyuki Nasuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090084433
    Abstract: A thin-film solar battery module comprising: a plurality of thin-film solar batteries; a supporting plate; and a frame, the thin-film solar battery having a string in which a plurality of thin-film photoelectric conversion elements, each formed by sequentially stacking a first electrode layer, a photoelectric conversion layer and a second electrode layer on a surface of an insulated substrate, are electrically connected in series, wherein the frame is attached to an outer circumference of the supporting plate in a condition that the plurality of thin-film solar batteries are arranged and fixed on the supporting plate.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Inventors: Toru Takeda, Yoshiyuki Nasuno, Masahiro Toyokawa, Yusuke Fukuoka
  • Publication number: 20080179702
    Abstract: A photoelectric conversion device includes a p-type layer, an i-type layer and an n-type layer each made of a silicon base semiconductor, stacked in this order, wherein the i-type layer contains n-type impurities in a concentration of 1.0×1016 to 2.0×1017 cm?3.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 31, 2008
    Inventors: Yoshiyuki Nasuno, Yasuaki Ishikawa, Takanori Nakano
  • Publication number: 20080173348
    Abstract: A stacked photoelectric conversion device includes a first photoelectric conversion layer, a second photoelectric conversion layer and a third photoelectric conversion layer each having a p-i-n junction and made of a silicon base semiconductor, stacked in this order from a light entrance side, wherein the first and the second photoelectric conversion layers have an i-type amorphous layer made of an amorphous silicon base semiconductor, respectively, and the third photoelectric conversion layer has an i-type microcrystalline layer made of a microcrystalline silicon base semiconductor.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 24, 2008
    Inventors: Yoshiyuki NASUNO, Yasuaki ISHIKAWA, Takanori NAKANO
  • Publication number: 20070163635
    Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group IIIb element into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.
    Type: Application
    Filed: January 9, 2007
    Publication date: July 19, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Kazuhito Nishimura
  • Publication number: 20070151596
    Abstract: A substrate 1 for a photoelectric conversion device includes a first transparent conductive layer 5 formed on at least a part of the surface region of a transparent substrate 3, the first transparent conductive layer 5 having at least an opening portion 7 exposing the substrate 3.
    Type: Application
    Filed: January 7, 2005
    Publication date: July 5, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Kazuhiko Nishimura, Takashi Hayakawa
  • Publication number: 20050229965
    Abstract: A photoelectric conversion device comprising: a pin-type photoelectric conversion layer constituted of a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer, wherein the p-type semiconductor layer contains silicon atoms and nitrogen atoms, which is possible to improve photoelectric conversion efficiency.
    Type: Application
    Filed: March 24, 2005
    Publication date: October 20, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhito Nishimura, Yoshiyuki Nasuno, Hiroshi Yamamoto, Yoshitaka Sugita
  • Patent number: 6787692
    Abstract: A solar cell substrate has irregularities on a surface which is in contact with a photo-electric conversion layer, and light is incident on the side of the irregularities. The height of the irregularities is set so that the root mean square height is in a range of 15 nm to 600 nm, and tan &thgr; is in a range of 0.10 to 0.30, where &thgr; is the angle of incline of the surface of the irregularities with respect to an average line of the irregularities. Light incident on the irregularities is scattered at the interface. This increases the optical path length and thus the quantity of light absorbed in the photo-electric conversion layer, resulting in improved efficiency. Additionally, the photo-electric conversion layer can be made thinner reducing deposit time and manufacturing cost. Further, collision of crystals is not incurred, thus preventing deterioration of photo-electric conversion efficiency which is caused by defects.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: September 7, 2004
    Assignees: National Institute of Advanced Industrial Science & Technology, Sharp Kabushiki Kaisha
    Inventors: Kenji Wada, Yoshiyuki Nasuno, Michio Kondo, Akihisa Matsuda
  • Publication number: 20020050289
    Abstract: A solar cell substrate of the present invention has irregularities on a surface which is in contact with a photo-electric conversion layer, and light is incident on the side of the irregularities. The height of the irregularities is set so that the root mean square height is in a range of 15 nm to 600 nm, and tan &thgr; is in a range of 0.10 to 0.30, where &thgr; is the angle of incline of the surface of the irregularities with respect to an average line of the irregularities. According to this arrangement, the light incident on the irregularities is scattered at the interface. This increases the optical path length and thus the quantity of light absorbed in the photo-electric conversion layer. As a result, photo-electric conversion efficiency can be improved and the photo-electric conversion layer can be made thinner, thereby greatly reducing deposit time and manufacturing cost required for the photo-electric conversion layer.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 2, 2002
    Inventors: Kenji Wada, Yoshiyuki Nasuno, Michio Kondo, Akihisa Matsuda