Patents by Inventor Yoshiyuki Ohshima

Yoshiyuki Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250028379
    Abstract: A novel semiconductor is provided. The semiconductor includes a first component, a second component, and an instruction portion. The first component includes a first memory circuit having a function of storing first setting information in a state where power is supplied, and a second memory circuit having a function of storing the first setting information in a state where power is not supplied. The second component includes a third memory circuit having a function of storing second setting information in a state where power is supplied, and a fourth memory circuit having a function of storing the second setting information in a state where power is not supplied. The instruction portion has a function of controlling whether power is supplied to each of the first component and the second component. Each of the second memory circuit and the fourth memory circuit includes a transistor including a metal oxide in a semiconductor layer where a channel is formed.
    Type: Application
    Filed: December 8, 2022
    Publication date: January 23, 2025
    Inventors: Yoshiyuki KUROKAWA, Masashi FUJITA, Kazuaki OHSHIMA
  • Publication number: 20250029648
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a register. The register includes a flip-flop and a plurality of data retention circuits. The flip-flop includes a first transistor in which a semiconductor layer including a channel formation region is silicon, an input terminal of the flip-flop is electrically connected to each of output terminals of the data retention circuits, and an output terminal of the flip-flop is electrically connected to each of input terminals of the data retention circuits. The data retention circuits include a second transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor, and when the second transistor is in a non-conduction state, the data retention circuits have a function of retaining a potential corresponding to data corresponding to a plurality of tasks.
    Type: Application
    Filed: December 5, 2022
    Publication date: January 23, 2025
    Inventors: Yoshiyuki KUROKAWA, Masashi FUJITA, Kazuaki OHSHIMA
  • Patent number: 11013797
    Abstract: A method for preventing or treating porcine epidemic diarrhea, the method including: administering a live vaccine of a porcine epidemic diarrhea virus and an adjuvant to a pig through oral administration or nasal administration; and administering an inactivated vaccine of the porcine epidemic diarrhea virus and an adjuvant to the pig through intramuscular administration.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: May 25, 2021
    Assignees: NIPPON INSTITUTE FOR BIOLOGICAL SCIENCE, NISSEIKEN CO., LTD.
    Inventors: Tetsuo Sato, Kazuki Oroku, Yoshiyuki Ohshima, Yoshiaki Furuya, Nobuyuki Tsutsumi
  • Publication number: 20190209676
    Abstract: A method for preventing or treating porcine epidemic diarrhea, the method including: administering a live vaccine of a porcine epidemic diarrhea virus and an adjuvant to a pig through oral administration or nasal administration; and administering an inactivated vaccine of the porcine epidemic diarrhea virus and an adjuvant to the pig through intramuscular administration.
    Type: Application
    Filed: July 24, 2017
    Publication date: July 11, 2019
    Inventors: Tetsuo Sato, Kazuki Oroku, Yoshiyuki Ohshima, Yoshiaki Furuya, Nobuyuki Tsutsumi