Abstract: PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: A voltage-controlled oscillating circuit according to the present invention includes: a bias voltage generating circuit outputting a bias voltage according to a control voltage; and a ring oscillator circuit receiving supply of the bias voltage to operate. The bias voltage generating circuit generates the bias voltage using a feedback circuit formed by an operational amplifier receiving supply of a power source voltage to operate. Therefore, an influence of a high frequency component overlapped on the power source voltage, that is an influence of noise, is suppressed, thereby enabling stable generation of an output clock having a small variation in phase.

Abstract: A pulse generation circuit (11) generates a pulse signal (S11) of “L” with a rise of a clock signal (CLOCK) as a trigger. A latch circuit (12) changes a latch signal (S12) fry “L” to “H” on the basis of the pulse signal (11) of “L”. Inverters (G10, G11) output a signal (XDEC) on the basis of the latch signal (S12). Even when the generation of the “L” pulse of the pulse signal (S11) is terminated and the pulse signal (S11) returns to “H”, the latch circuit (12) is in a data holding state to sustain the latch signal (S12) of “H” during a period while the signal READY takes “H”. With this constitution, it is possible to provide a semiconductor integrated circuit having a control unit which can output an operation control signal in synchronization with the clock signal without being constrained by the time length of “H” (“L”) period of the clock signal.

Abstract: A voltage-controlled oscillating circuit according to the present invention includes: a drive voltage generating circuit outputting a bias voltage according to a control voltage; and a ring oscillator circuit receiving supply of the bias voltage to operate. The drive voltage generating circuit generates the bias voltage using a feedback circuit formed by an operational amplifier receiving supply of a power source voltage to operate. Therefore, an influence of a high frequency component overlapped on the power source voltage, that is an influence of noise, is suppressed, thereby enabling stable generation of an output clock having a small variation in phase.

Abstract: A pulse generation circuit (11) generates a pulse signal (S11) of “L” with a rise of a clock signal (CLOCK) as a trigger. A latch circuit (12) changes a latch signal (S12) from “L” to “H” on the basis of the pulse signal (11) of “L”. Inverters (G10, G11) output a signal (XDEC) on the basis of the latch signal (S12). Even when the generation of the “L” pulse of the pulse signal (S11) is terminated and the pulse signal (S11) returns to “H”, the latch circuit (12) is in a data holding state to sustain the latch signal (S12) of “H” during a period while the signal READY takes “H”. With this constitution, it is possible to provide a semiconductor integrated circuit having a control unit which can output an operation control signal in synchronization with the clock signal without being constrained by the time length of “H” (“L”) period of the clock signal.

Abstract: There is provided a current mirror circuit which suppresses variations in an output current resulting from the Early effect. A pair of transistors (T1, T2) of a conventional current mirror circuit have gates connected to each other, and sources connected to each other, with the gate and drain of one of the transistors short-circuited. The source and drain of the other transistor (T2) on an output current side are connected to the source and gate of a transistor (T3), respectively. The sources of all of the transistors (T1, T2, T3) are commonly connected to a constant current circuit comprised of a bias voltage generating circuit (VB1) and a transistor (T4). A bias point is determined so that the increase/decrease in a current (Iout) causes the increase/decrease in a current (Icom), and the sizes of the respective transistors are designed.

Abstract: A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied.

Abstract: A memory card connector assembly superimposed on a substrate includes a plurality of memory card connectors stacked on top of each other whose contacts are to be connected to corresponding terminals of associated memory cards. The contacts of a lowermost memory card connector are soldered to the substrate, and the contacts of at least one upper memory card connector are connected to an FPC board.

Abstract: In the application instrument provided in accordance with the present invention, an operating member inserted in the middle cylinder so as to be movable backward and forward in the axial direction thereof is operated so that a valve mechanism provided in the front portion of the middle cylinder is operated to supply the penpoint with the applied liquid stored in the rear portion of the middle cylinder. The valve mechanism includes a valve seat having a valve hole, a valve spindle provided with a valve element for opening and closing the valve hole, and a stretchable member for moving the valve spindle backward and forward. The stretchable member is elongated and shortened in the axial direction of the middle cylinder as the bent portions of the bent arms are bent less and more, respectively. The operating member is disposed behind the valve mechanism.

Abstract: An apparatus for processing video signals receives an input digital video signal corresponding to a displayed image and occurring in successive samples derived at a sampling clock frequency. The input digital video signal is divided into successive groups of samples corresponding to successive intervals of time, each group being further divided into N sections of successive samples and the samples within each section corresponding to a defined area of the displayed image. The received samples are written into an addressable memory at selected write addresses and are read out from selected read addresses. The read addresses are generated so as to cause cyclically sequential read out of the N sections, with the samples being read out in the order of entry and starting from the initial samples in each of the N sections. The N sections read from the memory are supplied to respective latch circuits, the outputs of which constitute N channel signals.