Patents by Inventor Yoshiyuki Satoh

Yoshiyuki Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130249087
    Abstract: An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads.
    Type: Application
    Filed: April 22, 2013
    Publication date: September 26, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Kimio Nakamura, Takayoshi Matsumura, Yoshiyuki Satoh, Kuniko Ishikawa, Kenji Kobae
  • Patent number: 8381963
    Abstract: A compression-bonding apparatus includes a support stage and a pressing tool. The pressing tool includes a pressing stage, an elastic member and a plurality of bonding heads. The elastic member is held by the pressing stage. The plurality of bonding heads includes an upper surface attached to the elastic member and a lower surface facing an upper surface of the support stage.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Fujitsu Limited
    Inventors: Kimio Nakamura, Yoshiyuki Satoh, Kenji Kobae
  • Publication number: 20120230001
    Abstract: An electronic device includes an interposer, a first chip being mounted on a first surface of the interposer, the first chip having a first surface facing the first surface of the interposer and a second surface opposite to the first surface of the first chip, a second chip being mounted on a second surface of the interposer opposite to the first surface of the interposer, the second chip having a first surface facing the second surface of the interposer and a second surface opposite to the first surface of the second chip, a first metal plate being connected to the second surface of the first chip, a second metal surface being provided over the second surface of the second chip, and a via penetrating through the interposer and connected to the first metal plate and the second metal plate.
    Type: Application
    Filed: January 12, 2012
    Publication date: September 13, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuya TAKAHASHI, Kenji KOBAE, Shuichi TAKEUCHI, Yoshiyuki SATOH, Kimio NAKAMURA
  • Patent number: 8169075
    Abstract: According to an aspect of the invention, an electronic part includes a substrate having a first planar surface, a first bump affixed to the first planar surface of the substrate, a second bump affixed to the first planar surface of the substrate a predetermined distance from the first bump, a MEMS chip including a element, the MEMS chip coupled to the first bump and the second bump, the MEMS chip distanced from the first planar surface, an adhesive region bonding with the first bump, the substrate and the MEMS chip.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Takahashi, Kenji Kobae, Shuichi Takeuchi, Yoshiyuki Satoh, Hidehiko Kira, Takayoshi Matsumura
  • Publication number: 20120080219
    Abstract: A method of manufacturing an electronic device in which an electronic component is flip-chip mounted on a circuit board, the method includes supplying, on an electrode of the circuit board or a terminal of the electronic component, a first resin material of a thickness smaller than a gap between the circuit board and the electronic component, after supplying the first resin material, connecting the terminal to the electrode by melting a solder material disposed on the electrode or the terminal at a first temperature with keeping the terminal in contact with the electrode, after connecting the terminal to the electrode, filling the gap between the circuit board and the electronic component with a second resin material, and heating the second resin material at a second temperature lower than the first temperature.
    Type: Application
    Filed: August 12, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shuichi TAKEUCHI, Kenji KOBAE, Yoshiyuki SATOH, Naoki ISHIKAWA, Takeshi MIYAKOSHI, Tetsuya TAKAHASHI
  • Publication number: 20120080220
    Abstract: An electronic device includes a circuit board including a first electrode and a second electrode; and an electronic component including a first terminal and a second terminal, wherein the first electrode includes a first pad portion to which the first terminal is connected and a first protrusion portion disposed in a first direction in parallel with a straight line passing through the first electrode and the second electrode with respect to the first pad portion and being into contact with the first terminal, the second electrode includes a second pad portion to which the second terminal is connected and a second protrusion portion disposed in a second direction opposite to the first direction with respect to the second pad portion and being into contact with the second terminal.
    Type: Application
    Filed: August 2, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Kimio NAKAMURA, Shuichi TAKEUCHI, Yoshiyuki SATOH, Kenji KOBAE
  • Publication number: 20110079896
    Abstract: A semiconductor device fabrication method, comprising the steps of: forming a solder portion on an electrode of a substrate on which a semiconductor chip is to be mounted; applying a resin layer onto the substrate to a thickness such that a top region of the solder portion is exposed; curing the resin layer; providing a thermosetting underfill material over a region where the semiconductor chip is to be mounted; placing an electrode of the semiconductor chip face down on the solder portion in such a manner that the electrode faces the solder portion; and heating the underfill material and the solder portion.
    Type: Application
    Filed: September 28, 2010
    Publication date: April 7, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Yoshiyuki SATOH, Kenji KOBAE, Kimio NAKAMURA, Takayoshi MATSUMURA, Kuniko ISHIKAWA
  • Publication number: 20100327043
    Abstract: A compression-bonding apparatus includes a support stage and a pressing tool. The pressing tool includes a pressing stage, an elastic member and a plurality of bonding heads. The elastic member is held by the pressing stage. The plurality of bonding heads includes an upper surface attached to the elastic member and a lower surface facing an upper surface of the support stage.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kimio NAKAMURA, Yoshiyuki Satoh, Kenji Kobae
  • Publication number: 20100327435
    Abstract: An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kimio Nakamura, Takayoshi Matsumura, Yoshiyuki Satoh, Kuniko Ishikawa, Kenji Kobae
  • Patent number: 7687314
    Abstract: An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first adhesive agent, affixing the mounting substrate and electronic component, filling a space between the mounting substrate and the electronic component with a second adhesive agent under reduced pressure, and a second heating step of, from being under reduced pressure to being under atmospheric pressure, by pressing the heating head against the non-mounting surface of the electronic component, heating the electronic component, as well as hardening the second adhesive agent, melting the connection pads, and joining the connection pads and the bumps.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: March 30, 2010
    Assignee: Fujitsu Limited
    Inventors: Shuichi Takeuchi, Hidehiko Kira, Kenji Kobae, Yoshiyuki Satoh, Tetsuya Takahashi
  • Publication number: 20090243006
    Abstract: According to an aspect of the invention, an electronic part includes a substrate having a first planar surface, a first bump affixed to the first planar surface of the substrate, a second bump affixed to the first planar surface of the substrate a predetermined distance from the first bump, a MEMS chip including a element, the MEMS chip coupled to the first bump and the second bump, the MEMS chip distanced from the first planar surface, an adhesive region bonding with the first bump, the substrate and the MEMS chip.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU Limited
    Inventors: Tetsuya TAKAHASHI, Kenji Kobae, Shuichi Takeuchi, Yoshiyuki Satoh, Hidehiko Kira, Takayoshi Matsumura
  • Publication number: 20090170245
    Abstract: An electronic apparatus manufacturing method comprises applying a first adhesive agent to a mounting portion, a first heating, in such a way that connection pads and bumps, come into contact, by pressing a heating head against a non-mounting surface of the electronic component, heating the electronic component, hardening the first adhesive agent, affixing the mounting substrate and electronic component, filling a space between the mounting substrate and the electronic component with a second adhesive agent under reduced pressure, and a second heating step of,, from being under reduced pressure to being under atmospheric pressure, by pressing the heating head against the non-mounting surface of the electronic component, heating the electronic component, as well as hardening the second adhesive agent, melting the connection pads, and joining the connection pads and the bumps.
    Type: Application
    Filed: December 8, 2008
    Publication date: July 2, 2009
    Applicant: Fujitsu Limited
    Inventors: Shuichi TAKEUCHI, Hidehiko Kira, Kenji Kobae, Yoshiyuki Satoh, Tetsuya Takahashi
  • Patent number: 5999877
    Abstract: A traffic flow monitor apparatus which can monitor a traffic flow at high precision over a wide range from the position near a TV camera to the distant position regardless of traffic conditions. An image analysis area crossing a road of an overlooked road image received every predetermined cycle is analyzed, the characteristic portion of the front (rear) portion of the vehicle is registered as a template, the vehicle is tracked by a pattern-matching process while updating the template, and the size of the template is reduced (enlarge) depending on a change in apparent width of a lane during template updating. Since the characteristic portion of the front (rear) portion of the vehicle is registered, and the vehicle is tracked by the pattern-matching process, no reference image of a road portion on which no vehicle exists is required, and influence of approaching or overlapping of another vehicle can be reduced. A traffic flow can be monitored at high precision regardless of deserted traffic or crowded traffic.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: December 7, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Kazuya Takahashi, Tadaaki Kitamura, Yoshiyuki Satoh
  • Patent number: 5757287
    Abstract: An object recognition system using the image processing in which an area having a unique feature is extracted from an input image of an object, the unique image is registered in a shade template memory circuit as a shade template, the input image is searched for an image similar to the shade template registered by a shade pattern matching circuit, the position of an object is determined for each template, the speed and direction of movement of the object is determined from the positional information, and the results thereof are integrated by a separation/integration circuit, thereby recognizing the whole of the moving object.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: May 26, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tadaaki Kitamura, Yoshiki Kobayashi, Kunio Nakanishi, Masakazu Yahiro, Yoshiyuki Satoh, Toshiro Shibata, Takeshi Horie, Katsuyuki Yamamoto, Masao Takatoo, Haruki Inoue, Kazuyoshi Asada
  • Patent number: 5623580
    Abstract: A planning system for quickly forming the optimum plan for a given planning problem, includes a setting unit for accepting the given planning problem; an optimization unit for creating an objective function which expresses an item intended to be minimized or maximized in the planning problem, and for executing a process which minimizes or maximizes a value of the created objective function; a storage unit for storing therein, at least, constant values which are required for the optimizing process; and a display unit for displaying a processed result of the optimization unit.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: April 22, 1997
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Haruki Inoue, Hiroyuki Ichikawa, Hideo Yoshida, Yasuhiro Terada, Noboru Abe, Yoshiyuki Satoh, Masakazu Yahiro, Akemi Ohtsuki
  • Patent number: 5554983
    Abstract: An object recognition system using the image processing in which an area having a unique feature is extracted from an input image of an object, the unique image is registered in a shade template memory circuit as a shade template, the input image is searched for an image similar to the shade template registered by a shade pattern matching circuit, the position of an object is determined for each template, the speed and direction of movement of the object is determined from the positional information, and the results thereof are integrated by a separation/integration circuit, thereby recognizing the whole of the moving object.
    Type: Grant
    Filed: April 23, 1993
    Date of Patent: September 10, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tadaaki Kitamura, Yoshiki Kobayashi, Kunio Nakanishi, Masakazu Yahiro, Yoshiyuki Satoh, Toshiro Shibata, Takeshi Horie, Katsuyuki Yamamoto, Masao Takatoo, Haruki Inoue, Kazuyoshi Asada
  • Patent number: 5377308
    Abstract: A process control system for controlling a process exhibiting both linear behavior and non-linear behavior with a plurality of control quantities has a knowledge base storing therein universal facts, production rules including expert's empirical rules, meta rules describing flows of inferences, algorithm methods by mathematical expressions and membership functions referenced in fuzzy inference and a complex inference mechanism.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: December 27, 1994
    Assignees: Hitachi, Ltd., Hitachi Engineering Co.
    Inventors: Haruki Inoue, Motohisa Funabashi, Masakazu Yahiro, Yoshiyuki Satoh
  • Patent number: 5251285
    Abstract: A prediction control of a process containing a non-linear behavior is effected by predicting a transition of process quantities (control quantities) of an object to be controlled a predetermined time period after the current time to provide predicted values and by determining manipulation quantities of at least a control effector in accordance with a difference between the predicted values and predetermined target values of the controlled object. A quantitative operation is carried out arithmetically identifying a process as a linear behavior, and a fuzzy inference or qualitative operation, including a fuzzy rule based on empirical knowledge, is carried out for simulating a process, wherein for input process information and current manipulation quantities to be maintained, both operations parallelly determine predicted values of control quantities. A process behavior determination is arithmetically carried out to determine whether the process linearly behaves (i.e.
    Type: Grant
    Filed: June 7, 1991
    Date of Patent: October 5, 1993
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Haruki Inoue, Motohisa Funabashi, Masakazu Yahiro, Yoshiyuki Satoh
  • Patent number: 5051932
    Abstract: A process control system for controlling a process exhibiting both linear behavior and non-linear behavior with a plurality of control quantities has a knowledge base storing therein universal facts, production rules including expert's empirical rules, meta rules describing flows of inferences, algorithm methods by mathematical expressions and membership functions referenced in fuzzy inference and a complex inference mechanism.
    Type: Grant
    Filed: March 24, 1989
    Date of Patent: September 24, 1991
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Haruki Inoue, Motohisa Funabashi, Masakazu Yahiro, Yoshiyuki Satoh
  • Patent number: 4985333
    Abstract: The positive-working photosensitive composition useful as a material of photoresist comprises, in addition to a film-forming resin, such as a cresol novolak resin, and a photosensitive compound, such as an ester of a polyhydroxy benzophenone and 1,2-naphthoquinonediazido-5-sulfonic acid, an esterification product of curcumin with 1,2-naphthoquinone diazide sulfonic acid in a limited amount. The photosensitive composition is outstandingly insusceptible to the adverse influence of halation even when the photoresist layer is formed on a highly reflective aluminum-deposited surface of a substrate without decreasing the photosensitivity of the composition to actinic rays in the photolithographic process for the manufacture of semiconductor devices.
    Type: Grant
    Filed: July 27, 1989
    Date of Patent: January 15, 1991
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Nobuo Tokutake, Koichi Takahashi, Yoshiyuki Satoh, Hidekatsu Kohara, Toshimasa Nakayama