Patents by Inventor Yoshiyuki Shibahara

Yoshiyuki Shibahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286953
    Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 10, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Makoto KITAGAWA, Yoshiyuki SHIBAHARA, Haruhiko TERADA, Yotaro MORI
  • Publication number: 20200072315
    Abstract: A stopper is mounted on a vibrationproofing unit including a first bracket, a second bracket , an inside member being shaft shaped and in which the first bracket is fixed to the axial ends of the inside member, and a vibrationproofing base body including a rubber-like elastic body and coupling the outer circumferential face of the inside member and the inner circumferential face side of a tubular section of the second bracket. The stopper is plate shaped, includes a rubber-like elastic body, and includes a cushioning section disposed between the portions of the first bracket and the tubular section opposite in an axial direction of the tubular section. The cushioning section includes a thick wall section, a plurality of protrusion sections protruding from at least one face in a plate thickness direction of the thick wall section, and a thin wall section thinner than the thick wall section.
    Type: Application
    Filed: July 16, 2019
    Publication date: March 5, 2020
    Applicant: Toyo Tire Corporation
    Inventors: Yoshiyuki Seno, Tatsuya Oniwa, Ryou Shibahara
  • Publication number: 20200020411
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Application
    Filed: March 13, 2018
    Publication date: January 16, 2020
    Inventors: HARUHIKO TERADA, MAKOTO KITAGAWA, YOSHIYUKI SHIBAHARA, YOTARO MORI
  • Publication number: 20180293025
    Abstract: To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory cell by a predetermined unit with the unit data and to sequentially transmit the first periodic signal and the unit data. A controller-side interface circuit sequentially holds the transmitted unit data in holding units of a plurality of stages in synchronization with the periodic signal and sequentially reads and outputs the held unit data in synchronization with a second periodic signal.
    Type: Application
    Filed: October 8, 2015
    Publication date: October 11, 2018
    Inventors: Lui SAKAI, Yoshiyuki SHIBAHARA, Tetsuo YOSHIDA, Hidenobu KAKIOKA, Haruhiko TERADA
  • Patent number: 9792173
    Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 17, 2017
    Assignee: Sony Corporation
    Inventors: Naohiro Adachi, Yoshiyuki Shibahara, Yasushi Fujinami
  • Publication number: 20140372791
    Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.
    Type: Application
    Filed: May 7, 2014
    Publication date: December 18, 2014
    Applicant: Sony Corporation
    Inventors: Naohiro Adachi, Yoshiyuki Shibahara, Yasushi Fujinami
  • Patent number: 7477676
    Abstract: The present invention provides a spread spectrum clock generator that is capable of preventing phase jumps and jitters and suppressing the occurrence of Electro Magnetic Interference components and that can easily be applied to large scale integrated circuits. The spread spectrum clock generator can be configured with a filter, quantizer, fractional divider, and other elements. Also, this clock generator circuitry can be configured by combination of a delta-sigma ?? quantizer and factional divider so that sine wave modulation and random number modulation can be realized. Thereby, control with digital values can be performed. This clock generator prevents precipitous phase variations in the output high frequency clock and makes fine phase control possible. Consequently, EMI reduction by 20-30 dB can be expected.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: January 13, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masaru Kokubo, Yoshiyuki Shibahara
  • Patent number: 7138838
    Abstract: A variable loop bandwidth phase locked loop in which, upon input of a succession of signals “1”, no modulated signal degradation occurs and even at a high symbol rate, the reference signal frequency remains low and the sampling frequencies of a phase-frequency detector and a sigma delta circuit remain low. The phase locked loop comprises: a first modulator which transforms baseband signal TX_DATA into an integer signal for specifying a division number and sends it to a control terminal of a programmable divider; a second modulator which shapes an incoming baseband signal into a prescribed signal waveform and sends it to a voltage controlled oscillator; and a variable current charge pump which changes the loop bandwidth of the phase locked loop according to control signal CUR.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: November 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yoshiyuki Shibahara, Masaru Kokubo, Takashi Oshima
  • Patent number: 6870411
    Abstract: An object of this invention is to provide a phase synchronizing circuit capable of automatically adjusting a VCO such that the VCO satisfies a predetermined frequency range even in a frequency range in which the VCO oscillates by a leak current generated if a low threshold process is applied. The phase synchronizing circuit is composed of a PLL consisting of a phase comparator, a charge pump, a loop filter, a VCO, and a divider, and a calibration circuit for automatically adjusting a frequency range of the VCO. Before a convergence operation is started, a switch is closed in response to a signal Rst of the calibration circuit such that an output of the loop filter is leveled to the ground and the PLL is set to be an open loop. A VCO output Fo is set at an upper limit frequency or a lower limit frequency in response to a Vcal signal, and its frequency is measured by comparing its period with a period of a reference signal Fr, and signals Hb, Lb used for adjusting the frequency of the VCO are updated.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: March 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshiyuki Shibahara, Masaru Kokubo
  • Publication number: 20050008113
    Abstract: The present invention provides a spread spectrum clock generator that is capable of preventing phase jumps and jitters and suppressing the occurrence of Electro Magnetic Interference components and that can easily be applied to large scale integrated circuits. The spread spectrum clock generator can be configured with a filter, quantizer, fractional divider, and other elements. Also, this clock generator circuitry can be configured by combination of a delta-sigma ?? quantizer and factional divider so that sine wave modulation and random number modulation can be realized. Thereby, control with digital values can be performed. This clock generator prevents precipitous phase variations in the output high frequency clock and makes fine phase control possible. Consequently, EMI reduction by 20-30 dB can be expected.
    Type: Application
    Filed: June 9, 2004
    Publication date: January 13, 2005
    Inventors: Masaru Kokubo, Yoshiyuki Shibahara
  • Publication number: 20040207437
    Abstract: A variable loop bandwidth phase locked loop in which, upon input of a succession of signals “1”, no modulated signal degradation occurs and even at a high symbol rate, the reference signal frequency remains low and the sampling frequencies of a phase-frequency detector and a sigma delta circuit remain low. The phase locked loop comprises: a first modulator which transforms baseband signal TX_DATA into an integer signal for specifying a division number and sends it to a control terminal of a programmable divider; a second modulator which shapes an incoming baseband signal into a prescribed signal waveform and sends it to a voltage controlled oscillator; and a variable current charge pump which changes the loop bandwidth of the phase locked loop according to control signal CUR.
    Type: Application
    Filed: January 28, 2004
    Publication date: October 21, 2004
    Inventors: Yoshiyuki Shibahara, Masaru Kokubo, Takashi Oshima
  • Publication number: 20030042985
    Abstract: An object of this invention is to provide a phase synchronizing circuit capable of automatically adjusting a VCO such that the VCO satisfies a predetermined frequency range even in a frequency range in which the VCO oscillates by a leak current generated if a low threshold process is applied. The phase synchronizing circuit is composed of a PLL consisting of a phase comparator, a charge pump, a loop filter, a VCO, and a divider, and a calibration circuit for automatically adjusting a frequency range of the VCO. Before a convergence operation is started, a switch is closed in response to a signal Rst of the calibration circuit such that an output of the loop filter is leveled to the ground and the PLL is set to be an open loop. A VCO output Fo is set at an upper limit frequency or a lower limit frequency in response to a Vcal signal, and its frequency is measured by comparing its period with a period of a reference signal Fr, and signals Hb, Lb used for adjusting the frequency of the VCO are updated.
    Type: Application
    Filed: July 22, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiyuki Shibahara, Masaru Kokubo