Patents by Inventor Yoshiyuki Sugahara
Yoshiyuki Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10103059Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.Type: GrantFiled: July 28, 2016Date of Patent: October 16, 2018Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Yoshiyuki Sugahara, Takashi Tsutsumi, Youichi Makifuchi, Tsuyoshi Araoka, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
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Patent number: 10002952Abstract: A silicon carbide (SiC) semiconductor device, including a SiC substrate, a first SiC layer formed on the substrate, first and second impurity layers selectively formed in the first SiC layer, a second SiC layer formed on the first SiC layer, a third impurity layer selectively formed in the second SiC layer and on the second impurity layer, a third SiC layer formed on the second SiC layer, a fourth impurity layer selectively formed in the third SiC layer, a trench that penetrates the fourth impurity layer and the second and third SiC layers, a bottom thereof reaching the first impurity layer, and a gate electrode formed in the trench via a gate insulating film. The first SiC layer has first and second regions adjacent respectively to the first and second impurity layers on a side facing the substrate, an impurity concentration at the first region being lower than that at the second region.Type: GrantFiled: May 31, 2017Date of Patent: June 19, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yoshiyuki Sugahara, Keiji Okumura
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Publication number: 20180033876Abstract: A silicon carbide (SiC) semiconductor device, including a SiC substrate, a first SiC layer formed on the substrate, first and second impurity layers selectively formed in the first SiC layer, a second SiC layer formed on the first SiC layer, a third impurity layer selectively formed in the second SiC layer and on the second impurity layer, a third SiC layer formed on the second SiC layer, a fourth impurity layer selectively formed in the third SiC layer, a trench that penetrates the fourth impurity layer and the second and third SiC layers, a bottom thereof reaching the first impurity layer, and a gate electrode formed in the trench via a gate insulating film. The first SiC layer has first and second regions adjacent respectively to the first and second impurity layers on a side facing the substrate, an impurity concentration at the first region being lower than that at the second region.Type: ApplicationFiled: May 31, 2017Publication date: February 1, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yoshiyuki SUGAHARA, Keiji OKUMURA
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Patent number: 9839932Abstract: A surface chemical treatment apparatus provided with: a first conduit having an opening at one end and communicating with a liquid supply means at the other end; a second conduit having at one end an opening that surrounds the opening of the first conduit and communicating with a liquid suction means at the other end; and a moving mechanism for moving the openings of the first and second conduits relative to the solid phase surface, so as to make a surface chemical treatment possible in a fine pattern by allowing the patterning solution to be dispensed through the opening of the first conduit while allowing the solution to be suctioned up together with the surrounding liquid phase or gas phase medium through the opening of the second conduit that surrounds the opening of the first conduit and, thus, preventing seepage of the solution in all directions.Type: GrantFiled: February 14, 2013Date of Patent: December 12, 2017Assignees: SHIMADZU CORPORATION, TOKYO METROPOLITAN UNIVERSITY, WASEDA UNIVERSITYInventors: Katsumi Uchiyama, Hizuru Nakajima, Ming Yang, Hulie Zeng, Yoshiyuki Sugahara, Takahiro Nishimoto
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Publication number: 20160336224Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Yoshiyuki SUGAHARA, Takashi TSUTSUMI, Youichi MAKIFUCHI, Tsuyoshi ARAOKA, Kenji FUKUDA, Shinsuke HARADA, Mitsuo OKAMOTO
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Publication number: 20150376796Abstract: A surface chemical treatment apparatus provided with: a first conduit having an opening at one end and communicating with a liquid supply means at the other end; a second conduit having at one end an opening that surrounds the opening of the first conduit and communicating with a liquid suction means at the other end; and a moving mechanism for moving the openings of the first and second conduits relative to the solid phase surface, so as to make a surface chemical treatment possible in a fine pattern by allowing the patterning solution to be dispensed through the opening of the first conduit while allowing the solution to be suctioned up together with the surrounding liquid phase or gas phase medium through the opening of the second conduit that surrounds the opening of the first conduit and, thus, preventing seepage of the solution in all directions.Type: ApplicationFiled: February 14, 2013Publication date: December 31, 2015Applicants: SHIMADZU CORPORATION, WASEDA UNIVERSITY, TOKYO METROPOLITAN UNIVERSITYInventors: Katsumi UCHIYAMA, Hizuru NAKAJIMA, Ming YANG, Hulie ZENG, Yoshiyuki SUGAHARA, Takahiro NISHIMOTO
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Publication number: 20100110536Abstract: A small-sized, highly efficient optical amplifier having a PLZT optical waveguide layer to which a rare earth element is added, and a method for manufacturing the same are provided. Disclosed is an optical amplifier including an optical waveguide layer, the optical waveguide layer including Pb1-xLax(ZryTi1-y)1-x/4 O3 (PLZT: 0<x<0.3, 0<y<1.0), being doped with Yb (ytterbium) in an amount of from 0.2 mol % to 11.0 mol %, and being a single crystal film formed by solid-phase epitaxial growth.Type: ApplicationFiled: February 5, 2008Publication date: May 6, 2010Applicant: EpiPHOTONICS CORP.Inventors: Keiichi Nashimoto, Yoshiyuki Sugahara
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Patent number: 7554886Abstract: A disk access device records to and plays back from a disk on which data recording is performed according to the ZCLV format, and includes a head that reads/writes data from/to the disk. The disk access device calculates a deferment time period that begins upon completion of data reading/writing in the user area of a currently accessed zone and ends when the head enters a predetermined area of the guard track zone following the user area, and a setting time period for performing settings for data reading/writing in the zone to be accessed next. If the deferment time period is shorter than the setting time period, the disk access device moves the head back, when data reading or writing in the currently accessed zone ends, to a position such that the setting time period ends before the head advancing from the position arrives at the predetermined area.Type: GrantFiled: February 16, 2007Date of Patent: June 30, 2009Assignee: Panasonic CorporationInventors: Kiyoshi Masaki, Kazuhiko Miyazaki, Yoshiyuki Sugahara
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Patent number: 7526176Abstract: An optical amplifier including an optical waveguide layer (for example channel-shaped optical waveguide layer) including Pb1?xLax(ZryTi1?y)1?x/4O3(PLZT: 0<x<0.3, 0<y<1.0) doped with a rare earth element at an amount of 0.2 mol % to 11.0 mol %, the optical waveguide layer (for example channel-shaped optical waveguide layer) being formed as a single crystal film by solid-phase epitaxial growth.Type: GrantFiled: March 22, 2007Date of Patent: April 28, 2009Assignee: EpiPhotonics Corp.Inventors: Keiichi Nashimoto, Yoshiyuki Sugahara
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Publication number: 20090036687Abstract: A multinuclear complex comprising a plurality of metal atoms and a ligand L coordinating to the metal atoms, and satisfying the following conditions (i), (ii), (iii) and (iv): (i) The ligand L has a monovalent group represented by the following general formula (1) and/or a divalent group represented by the following general formula (2), (ii) The ligand L has at least 5 coordination atoms bonding to the metal atom, (iii) At least one of the coordination atoms bonds to two of the metal atoms, or the minimum number of covalent bonds between any two selected coordination atoms is 1-5, and (iv) The ligand L is soluble in the solvent.Type: ApplicationFiled: February 8, 2007Publication date: February 5, 2009Inventors: Yoshiyuki Sugahara, Takeshi Ishiyama, Hideyuki Higashimura
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Publication number: 20070237483Abstract: An optical amplifier including an optical waveguide layer (for example channel-shaped optical waveguide layer) including Pb1-xLax(ZryTi1-y)1-x/4 O3 (PLZT: 0<x<0.3, 0<y<1.0) doped with a rare earth element at an amount of 0.2 mol % to 11.0 mol %, the optical waveguide layer (for example channel-shaped optical waveguide layer) being formed as a single crystal film by solid-phase epitaxial growth.Type: ApplicationFiled: March 22, 2007Publication date: October 11, 2007Inventors: Keiichi Nashimoto, Yoshiyuki Sugahara
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Publication number: 20070201318Abstract: A disk access device records to and plays back from a disk on which data recording is performed according to the ZCLV format, and includes a head that reads/writes data from/to the disk. The disk access device calculates a deferment time period that begins upon completion of data reading/writing in the user area of a currently accessed zone and ends when the head enters a predetermined area of the guard track zone following the user area, and a setting time period for performing settings for data reading/writing in the zone to be accessed next. If the deferment time period is shorter than the setting time period, the disk access device moves the head back, when data reading or writing in the currently accessed zone ends, to a position such that the setting time period ends before the head advancing from the position arrives at the predetermined area.Type: ApplicationFiled: February 16, 2007Publication date: August 30, 2007Inventors: Kiyoshi Masaki, Kazuhiko Miyazaki, Yoshiyuki Sugahara
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Publication number: 20070184617Abstract: There is provided a semiconductor device having a high breakdown voltage and a high reliability in which a gate insulating film having a film thickness of good uniformity is formed inside a trench. An HTO is formed on an inner wall of a trench in an Si substrate by a reduced pressure CVD method and, thereafter, a thermally oxidized film is formed on an interface between the HTO and the Si substrate by performing a thermal oxidation treatment (Samples A and C). By performing these procedures as described above, the gate insulating film in which local thinning of the film is suppressed, film thickness is of good uniformity and an interface state density is low can be formed inside the trench. A semiconductor device, which has a trench gate structure, of a high quality and a high reliability having no reduction in the breakdown voltage in which a lifetime comes to be substantially longer compared with that (Sample B) in which the gate insulating film is formed only with a thermally oxidized film can be realized.Type: ApplicationFiled: March 4, 2005Publication date: August 9, 2007Applicant: FUJI ELECTRIC HOLDINGS CO., INC.Inventors: Masaaki Ogino, Yoshiyuki Sugahara
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Publication number: 20070104042Abstract: A media drive, a computer system, and a media drive control method, in which insertion/ejection of a removable medium into/from a media drive being in a sleep mode that is a power saving mode of operation can be detected, and the power consumptions of the media drive and host computer can be still more saved. When a CD-ROM drive (2) being in the sleep mode detects a change of status of a CD-ROM, such as insertion or ejection thereof, it notifies a personal computer (1) of the CD-ROM status change by using a hardware interrupt signal without polling. Thus, the status of CD-ROM insertion/ejection into/from the CD-ROM drive (2) can be grasped from the personal computer (1) to place the CD-ROM drive (2) in the sleep mode when the CD-ROM needs not be driven or in a normal mode of operation when it needs to be driven.Type: ApplicationFiled: January 19, 2005Publication date: May 10, 2007Inventors: Yoshiyuki Sugahara, Keiichi Osaka, Taisuke Miyoshi
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Patent number: 5607875Abstract: A method for separating a joined substrate type wafer, which wafer is composed of a pair of semiconductor substrates joined through an insulation film, utilizes dielectrics through simple processing steps. Trenches for separating a semiconductor substrate with dielectrics are dug from the surface of the substrate and a dielectrics film is deposited on the surface of the substrate including the trenches. Then poly-crystalline silicon is grown by CVD to a thickness of about 0.5 .mu.m, which is deep enough to fill the trenches. The process time for growing poly-crystalline silicon is shortened, and the processing step for removing the poly-crystalline silicon deposited on the unwanted areas is eliminated by growing the poly-crystalline silicon in the trenches but not on the crystalline surface of semiconductor regions based on the growth rate dependence of the poly-crystalline silicon on the crystallinity of the surface on which the poly-crystalline silicon is grown.Type: GrantFiled: May 31, 1995Date of Patent: March 4, 1997Assignee: Fuji Electric Co., Ltd.Inventors: Masato Nishizawa, Shinichi Hashimoto, Yoshiyuki Sugahara
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Patent number: 5572179Abstract: A thin film transformer which is fabricated on a substrate includes first and second thin film coils. One of the coils includes either of at least two spiral shaped coil parts that are disposed below an insulation layer and either of at least two spiral shaped coil parts that are disposed above the insulation layer, the coil parts being connected through a connection hole in the insulation layer, with terminals for the coil being located outside the outer loops of the coil parts. The other of the coils includes other coil parts that are connected through a connection hole in the insulation layer, with terminals again being located outside the outer loops of the coil parts. With this configuration, the first and second thin film coils have terminals that are located outside of the outer loops of the coils. Side-by-side transformers whose primaries and secondaries are connected so as to form a single transformer are also disclosed.Type: GrantFiled: January 10, 1995Date of Patent: November 5, 1996Assignee: Fuji Electric Co., Ltd.Inventors: Naoki Ito, Tsuneo Watanabe, Yoshiyuki Sugahara, Toshio Komori
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Patent number: 5420558Abstract: A thin film transformer which is fabricated on a substrate includes first and second thin film coils. One of the coils includes either of at least two spiral shaped coil parts that are disposed below an insulation layer and either of at least two spiral shaped coil parts that are disposed above the insulation layer, the coil parts being connected through a connection hole in the insulation layer, with terminals for the coil being located outside the outer loops of the coil parts. The other of the coils includes other coil parts that are connected through a connection hole in the insulation layer, with terminals again being located outside the outer loops of the coil parts. With this configuration, the first and second thin film coils have terminals that are located outside of the outer loops of the coils. Side-by-side transformers whose primaries and secondaries are connected so as to form a single transformer are also disclosed.Type: GrantFiled: May 26, 1993Date of Patent: May 30, 1995Assignee: Fuji Electric Co., Ltd.Inventors: Naoki Ito, Tsuneo Watanabe, Yoshiyuki Sugahara, Toshio Komori
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Patent number: D407409Type: GrantFiled: January 5, 1996Date of Patent: March 30, 1999Assignee: SMC CorporationInventors: Mitsuo Masuda, Yoshiyuki Sugahara