Patents by Inventor Yoshiyuki Tonami

Yoshiyuki Tonami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879861
    Abstract: A bias circuit of an amplifying device including amplifying circuits and a bypass circuit responding to a first control signal, includes a first bias circuit, a second bias circuit, and a compensating circuit. The first bias circuit is configured to supply a first base bias voltage to a first amplifying circuit of the amplifying circuits in response to a second control signal. The second bias circuit is configured to supply a second base bias voltage to a second amplifying circuit of the amplifying circuits in response to a third control signal. The compensating circuit is connected to either one or both of the first bias circuit and the second bias circuit, and configured to vary an impedance in response to a fourth control signal, and compensate for either one or both of the first base bias voltage and the second base bias voltage based on the varied impedance.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 29, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Wook Park, Dae Hee No, Hyun Jun Kim, Bo Hyun Hwang, Jun Goo Won, Da Hye Park, Sung Hwan Park, Ki Joong Kim, Yoshiyuki Tonami
  • Publication number: 20200287510
    Abstract: A bias circuit of an amplifying device including amplifying circuits and a bypass circuit responding to a first control signal, includes a first bias circuit, a second bias circuit, and a compensating circuit. The first bias circuit is configured to supply a first base bias voltage to a first amplifying circuit of the amplifying circuits in response to a second control signal. The second bias circuit is configured to supply a second base bias voltage to a second amplifying circuit of the amplifying circuits in response to a third control signal. The compensating circuit is connected to either one or both of the first bias circuit and the second bias circuit, and configured to vary an impedance in response to a fourth control signal, and compensate for either one or both of the first base bias voltage and the second base bias voltage based on the varied impedance.
    Type: Application
    Filed: June 28, 2019
    Publication date: September 10, 2020
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Wook PARK, Dae Hee NO, Hyun Jun KIM, Bo Hyun HWANG, Jun Goo WON, Da Hye PARK, Sung Hwan PARK, Ki Joong KIM, Yoshiyuki TONAMI
  • Patent number: 10547307
    Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun Goo Won, Youn Suk Kim, Yoshiyuki Tonami, Ki Joong Kim
  • Publication number: 20180294809
    Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun Goo WON, Youn Suk KIM, Yoshiyuki TONAMI, Ki Joong KIM
  • Patent number: 10027320
    Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: July 17, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun Goo Won, Youn Suk Kim, Yoshiyuki Tonami, Ki Joong Kim
  • Publication number: 20160134245
    Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.
    Type: Application
    Filed: October 19, 2015
    Publication date: May 12, 2016
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jun Goo WON, Youn Suk KIM, Yoshiyuki TONAMI, Ki Joong KIM
  • Patent number: 7316783
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: January 8, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 7144618
    Abstract: A multilayer composite includes an insulating substrate and patterned conductive layers and insulating layers alternately laminated on the insulating substrate. In a laminating process, a correcting insulating layer is formed on a laminate when a predetermined number of layers are laminated or when a predetermined degree of warpage of the laminate is detected by monitoring. The correcting insulating layer has a different composition from that of the other insulating layers to correct the warpage of the laminate.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: December 5, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yuji Sugiyama, Michiaki Iha
  • Publication number: 20050104218
    Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.
    Type: Application
    Filed: November 19, 2004
    Publication date: May 19, 2005
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Mitsunori Hatada
  • Patent number: 6838377
    Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: January 4, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Mitsunori Hatada
  • Publication number: 20040262032
    Abstract: A multilayer composite includes an insulating substrate and patterned conductive layers and insulating layers alternately laminated on the insulating substrate. In a laminating process, a correcting insulating layer is formed on a laminate when a predetermined number of layers are laminated or when a predetermined degree of warpage of the laminate is detected by monitoring. The correcting insulating layer has a different composition from that of the other insulating layers to correct the warpage of the laminate.
    Type: Application
    Filed: October 9, 2003
    Publication date: December 30, 2004
    Inventors: Yoshiyuki Tonami, Yuji Sugiyama, Michiaki Iha
  • Publication number: 20040245110
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Application
    Filed: July 7, 2004
    Publication date: December 9, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 6808641
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: October 26, 2004
    Assignee: Murata Manufacturing Co., Ltd
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 6727571
    Abstract: A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: April 27, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuji Sugiyama, Yoshiyuki Tonami, Masahiko Kawaguchi
  • Publication number: 20030098496
    Abstract: A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 29, 2003
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yuji Sugiyama, Yoshiyuki Tonami, Masahiko Kawaguchi
  • Publication number: 20020125566
    Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.
    Type: Application
    Filed: March 5, 2002
    Publication date: September 12, 2002
    Inventors: Yoshiyuki Tonami, Mitsunori Hatada
  • Publication number: 20010008225
    Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 19, 2001
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
  • Patent number: 5818283
    Abstract: In an FET switch for controllably allowing and inhibiting passage of an input signal in ON state and OFF state, respectively, FETs are connected in a multi-stage configuration. A control voltage adjusting circuit is connected between a gate and one of a drain and a source of each FET. The control voltage adjusting circuit adjusts a gate-source voltage so as to follow the variation of a drain-source voltage. The input voltage applied to the FET switch in OFF state is divided by the plurality of FETs. Since the variation of the gate-source voltage follows the variation of the drain-source voltage, the FET switch is hardly influenced by an amplitude of the input signal.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: October 6, 1998
    Assignee: Japan Radio Co., Ltd.
    Inventors: Yoshiyuki Tonami, Goro Yoshida, Kazuo Yamashita