Abstract: A solid-state battery package that includes: a substrate; and a solid-state battery on the substrate. The solid-state battery has: a battery element having a positive electrode layer, a negative electrode layer, and a solid electrolyte; and an end-face electrode on an end face of the battery element and connected to one of the positive or negative electrode layers. The substrate has a substrate electrode layer on a main surface thereof, and at least a first side surface of the substrate electrode layer and a first end face of the end-face electrode are substantially on an identical line in a sectional view, a distance between the first side surface and a second side surface of the substrate electrode layer is equal to or more than a minimum distance between the first end face and an end surface of the positive or negative electrode layer that the end-face electrode is not connected.

Abstract: A bias circuit of an amplifying device including amplifying circuits and a bypass circuit responding to a first control signal, includes a first bias circuit, a second bias circuit, and a compensating circuit. The first bias circuit is configured to supply a first base bias voltage to a first amplifying circuit of the amplifying circuits in response to a second control signal. The second bias circuit is configured to supply a second base bias voltage to a second amplifying circuit of the amplifying circuits in response to a third control signal. The compensating circuit is connected to either one or both of the first bias circuit and the second bias circuit, and configured to vary an impedance in response to a fourth control signal, and compensate for either one or both of the first base bias voltage and the second base bias voltage based on the varied impedance.

Abstract: A bias circuit of an amplifying device including amplifying circuits and a bypass circuit responding to a first control signal, includes a first bias circuit, a second bias circuit, and a compensating circuit. The first bias circuit is configured to supply a first base bias voltage to a first amplifying circuit of the amplifying circuits in response to a second control signal. The second bias circuit is configured to supply a second base bias voltage to a second amplifying circuit of the amplifying circuits in response to a third control signal. The compensating circuit is connected to either one or both of the first bias circuit and the second bias circuit, and configured to vary an impedance in response to a fourth control signal, and compensate for either one or both of the first base bias voltage and the second base bias voltage based on the varied impedance.

Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

Abstract: A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: A multilayer composite includes an insulating substrate and patterned conductive layers and insulating layers alternately laminated on the insulating substrate. In a laminating process, a correcting insulating layer is formed on a laminate when a predetermined number of layers are laminated or when a predetermined degree of warpage of the laminate is detected by monitoring. The correcting insulating layer has a different composition from that of the other insulating layers to correct the warpage of the laminate.

Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

Abstract: A multilayer composite includes an insulating substrate and patterned conductive layers and insulating layers alternately laminated on the insulating substrate. In a laminating process, a correcting insulating layer is formed on a laminate when a predetermined number of layers are laminated or when a predetermined degree of warpage of the laminate is detected by monitoring. The correcting insulating layer has a different composition from that of the other insulating layers to correct the warpage of the laminate.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.

Abstract: A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.

Abstract: In the production of a high frequency circuit chip in which a wiring pattern is disposed on a substrate having a through-hole, a connecting electrode of the through-hole is formed by filling electrically conductive paste into a perforation and firing it, and the wiring pattern is formed by a lift-off method. Moreover, at least the surface of the substrate for the wiring pattern to be formed thereon is mirror-polished, and thereafter, the wiring pattern is formed on the mirror-polished surface by the lift-off method.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: In an FET switch for controllably allowing and inhibiting passage of an input signal in ON state and OFF state, respectively, FETs are connected in a multi-stage configuration. A control voltage adjusting circuit is connected between a gate and one of a drain and a source of each FET. The control voltage adjusting circuit adjusts a gate-source voltage so as to follow the variation of a drain-source voltage. The input voltage applied to the FET switch in OFF state is divided by the plurality of FETs. Since the variation of the gate-source voltage follows the variation of the drain-source voltage, the FET switch is hardly influenced by an amplitude of the input signal.