Patents by Inventor Yoshiyuki Tsunoda

Yoshiyuki Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Defective-ratio predicting method, defective-ratio predicting program, managing method for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device
    Patent number: 8612811
    Abstract: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Kazuyuki Tsunokuni
  • DEFECTIVE-RATIO PREDICTING METHOD, DEFECTIVE-RATIO PREDICTING PROGRAM, MANAGING METHOD FOR SEMICONDUCTOR MANUFACTURING APPARATUS, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
    Publication number: 20110172806
    Abstract: In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.
    Type: Application
    Filed: September 4, 2009
    Publication date: July 14, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Kazuyuki Tsunokuni