Abstract: A PLL system includes a phase comparator, charge pump, LPF, VCO, 1/N frequency divider, CRT drive circuit, and arithmetic unit. The charge pump outputs a charge pump signal in accordance with the phase error signal output from the phase comparator. The current capacity of the charge pump is controlled to keep a PLL loop gain constant by compensation for a variation in PLL loop gain due to a change in a frequency division ratio 1/N in the frequency divider.

Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Abstract: There is disclosed a phase-locked loop (PLL) circuit for use in an improved deflection correction circuit for a larger and flat display device. The PLL circuit has a phase comparator circuit, a filter, and a voltage-controlled oscillator (VCO) connected in series in this order. The output signal from the VCO is fed back to the phase comparator circuit. The PLL circuit further includes a period-detecting circuit for detecting the period of an externally applied signal and a frequency divider circuit. This frequency divider circuit divides the frequency of the output signal from the VCO according to the period detected by the period-detecting circuit and feeds the resulting signal back to the VCO.

Abstract: A PLL system includes a phase comparator, charge pump, LPF, VCO, 1/N frequency divider, CRT drive circuit, and arithmetic unit. The phase comparator compares the phase of an input horizontal sync signal with that of a comparison signal. The charge pump outputs a charge pump signal in accordance with the phase error signal output from the phase comparator. The LPF converts the charge pump signal from the charge pump into a voltage control signal. The VCO changes the oscillation frequency in accordance with the voltage control signal output from the LPF. The 1/N frequency divider performs 1/N frequency division of the frequency signal output from the voltage-controlled oscillator in accordance with a control signal. The CRT drive circuit performs deflection processing in a CRT on the basis of an output from the frequency divider and outputs, to the phase comparator, a comparison signal based on a reference signal for a display system which is generated by CRT deflection processing.

Abstract: A PLL circuit for a CRT monitor horizontal drive signal includes a phase comparator, charge pump, LPF, VCO, frequency divider, and switching circuit. The phase comparator compares the phase of an input horizontal sync signal with that of an internal reference signal and outputs a phase difference signal. The charge pump outputs a charge pump signal in accordance with the phase difference signal. The LPF converts the charge pump signal into a voltage control signal. The oscillation frequency of the VCO is controlled in accordance with the voltage control signal output. The frequency divider frequency-divides an output from the voltage controlled oscillator and outputs a CRT monitor horizontal drive signal phase-locked by a horizontal sync signal. The CRT monitor horizontal drive signal is used to generate the internal reference signal.

Abstract: A phase locked loop makes a system clock signal synchronous to a horizontal synchronizing signal for a display unit, and a lock-in detecting circuit monitors said phase locked loop to see whether or not a phase difference takes place between the system clock signal and the horizontal synchronizing signal, wherein the lock-in detecting circuit measures the unlocked state between the system clock signal and the horizontal synchronizing signal in a window defined in a vertical synchronizing period and, thereafter, compares the time period of the unlocked state with a critical value to see whether or not the unlocked state is due to a temporary phenomenon or a phase difference to be corrected so that an detecting signal of the lock-in detecting circuit is reliable.