Patents by Inventor Yoshiyuki Yonezawa
Yoshiyuki Yonezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958392Abstract: A seat pad manufacturing method is provided. The method includes disposing a sheet member inside a foaming mold for shaping a seat pad, then injecting a foaming resin material into the foaming mold and foaming a resin foamed body through mold clamping, and demolding the resin foamed body in a state in which the sheet member is buried in the resin foamed body. Both end parts of the sheet member in the right-left direction and both end parts of the sheet member in the extending direction are each temporarily fastened to the surface of the mold through a fastener. The foaming resin material is injected into a space between the mold surface and the sheet member. A central part of the sheet member deforms into a shape curved in a convex shape as the sheet member is pressed upward through expansion of the foaming resin material.Type: GrantFiled: December 6, 2022Date of Patent: April 16, 2024Assignee: Archem Inc.Inventors: Yukiko Yamaguchi, Taisuke Yonezawa, Yoshiyuki Takahashi
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Publication number: 20220123112Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.Type: ApplicationFiled: November 30, 2021Publication date: April 21, 2022Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATIONInventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI
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Patent number: 11282919Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.Type: GrantFiled: February 15, 2019Date of Patent: March 22, 2022Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATIONInventors: Ryoji Kosugi, Kazuhiro Mochizuki, Kohei Adachi, Manabu Takei, Yoshiyuki Yonezawa
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Publication number: 20210111245Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.Type: ApplicationFiled: February 15, 2019Publication date: April 15, 2021Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, FUJI ELECTRIC CO., LTD., Mitsubishi Electric CorporationInventors: Ryoji KOSUGI, Kazuhiro MOCHIZUKI, Kohei ADACHI, Manabu TAKEI, Yoshiyuki YONEZAWA
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Patent number: 10868122Abstract: During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 ?m from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.Type: GrantFiled: May 31, 2019Date of Patent: December 15, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takeshi Tawara, Koji Nakayama, Yoshiyuki Yonezawa, Hidekazu Tsuchida, Koichi Murata
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Publication number: 20190393312Abstract: During epitaxial growth of an n?-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n?-type lifetime reduced layer is selectively formed in the n?-type drift layer. The n?-type lifetime reduced layer is disposed at a depth that is more than 5 ?m from a pn junction surface between a p-type anode layer and the n?-type drift layer in a direction toward a cathode side, and the n?-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n?-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is ? times a thickness of the n?-type drift layer. A vanadium concentration of the n?-type lifetime reduced layer is 1/100 to ? of a nitrogen concentration of the n?-type lifetime reduced layer.Type: ApplicationFiled: May 31, 2019Publication date: December 26, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takeshi TAWARA, Koji Nakayama, Yoshiyuki Yonezawa, Hidekazu Tsuchida, Koichi Murata
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Patent number: 10354867Abstract: A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.Type: GrantFiled: September 22, 2017Date of Patent: July 16, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hidekazu Tsuchida, Tetsuya Miyazawa, Yoshiyuki Yonezawa, Tomohisa Kato, Kazutoshi Kojima, Takeshi Tawara, Akihiro Otsuki
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Patent number: 10026610Abstract: Provided is a method of manufacturing a silicon carbide semiconductor device with a long carrier lifetime without carrying out an additional step after a SiC single crystal substrate is fabricated using a chemical vapor deposition method. The silicon carbide semiconductor device manufacturing method includes (a) growing a silicon carbide single crystal film at a first temperature on a silicon carbide semiconductor substrate using chemical vapor deposition; (b) cooling the silicon carbide semiconductor substrate from the first temperature to a second temperature, which is lower than the first temperature, in an atmosphere of a carbon-containing gas after growing the silicon carbide crystal film; and (c) subsequently cooling the silicon carbide semiconductor substrate to a third temperature, which is lower than the second temperature, in a hydrogen gas atmosphere.Type: GrantFiled: April 9, 2015Date of Patent: July 17, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa
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Publication number: 20180012758Abstract: A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hidekazu TSUCHIDA, Tetsuya MIYAZAWA, Yoshiyuki YONEZAWA, Tomohisa KATO, Kazutoshi KOJIMA, Takeshi TAWARA, Akihiro OTSUKl
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Patent number: 9856582Abstract: A method is disclosed with provides stable growth of SiC single crystals, particularly 4H—SiC single crystals, with an effective crystal growth rate for a prolonged time even at a low temperature range of 2000° C. or lower. A raw material containing Si, Ti and Ni is charged into a crucible made of graphite and heat-melted to obtain a solvent. At the same time, C is dissolved out from the crucible into the solvent to obtain a melt. A SiC seed crystal substrate is then brought into contact with the melt such that SiC is supersaturated in the melt in the vicinity of the surface of the SiC seed crystal substrate, thereby allowing growth and production of an SiC single crystal on the SiC seed crystal substrate.Type: GrantFiled: March 23, 2012Date of Patent: January 2, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Mina Ryo, Yoshiyuki Yonezawa, Takeshi Suzuki
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Patent number: 9418840Abstract: Silicon-containing gas, carbon-containing gas, and chlorine-containing gas are introduced into a reacting furnace. Next, a SiC epitaxial film is grown on the front surface of a 4H-SiC substrate by a halide CVD method in a mixed gas atmosphere made of the plurality of gasses introduced. In the SiC epitaxial film growing, a SiC epitaxial film of a first predetermined thickness is grown at a first growth rate. The first growth rate is increased from an initial growth rate to a higher growth rate. Furthermore, the SiC epitaxial film is grown, at a second growth rate, until the thickness of the SiC epitaxial film reaches a second predetermined thickness. By so doing, it is possible to improve the crystallinity of a silicon carbide semiconductor film grown in a gas atmosphere containing halide.Type: GrantFiled: September 3, 2015Date of Patent: August 16, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa
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Patent number: 9257544Abstract: A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches.Type: GrantFiled: March 31, 2015Date of Patent: February 9, 2016Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE and TECHNOLOGYInventors: Manabu Takei, Yoshiyuki Yonezawa
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Publication number: 20150380243Abstract: Silicon-containing gas, carbon-containing gas, and chlorine-containing gas are introduced into a reacting furnace. Next, a SiC epitaxial film is grown on the front surface of a 4H-SiC substrate by a halide CVD method in a mixed gas atmosphere made of the plurality of gasses introduced. In the SiC epitaxial film growing, a SiC epitaxial film of a first predetermined thickness is grown at a first growth rate. The first growth rate is increased from an initial growth rate to a higher growth rate. Furthermore, the SiC epitaxial film is grown, at a second growth rate, until the thickness of the SiC epitaxial film reaches a second predetermined thickness. By so doing, it is possible to improve the crystallinity of a silicon carbide semiconductor film grown in a gas atmosphere containing halide.Type: ApplicationFiled: September 3, 2015Publication date: December 31, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki KAWADA, Yoshiyuki YONEZAWA
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Publication number: 20150311328Abstract: A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches.Type: ApplicationFiled: March 31, 2015Publication date: October 29, 2015Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, FUJI ELECTRIC CO., LTD.Inventors: Manabu Takei, Yoshiyuki Yonezawa
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Publication number: 20150214049Abstract: Provided is a method of manufacturing a silicon carbide semiconductor device with a long carrier lifetime without carrying out an additional step after a SiC single crystal substrate is fabricated using a chemical vapor deposition method. The silicon carbide semiconductor device manufacturing method includes (a) growing a silicon carbide single crystal film at a first temperature on a silicon carbide semiconductor substrate using chemical vapor deposition; (b) cooling the silicon carbide semiconductor substrate from the first temperature to a second temperature, which is lower than the first temperature, in an atmosphere of a carbon-containing gas after growing the silicon carbide crystal film; and (c) subsequently cooling the silicon carbide semiconductor substrate to a third temperature, which is lower than the second temperature, in a hydrogen gas atmosphere.Type: ApplicationFiled: April 9, 2015Publication date: July 30, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki KAWADA, Yoshiyuki YONEZAWA
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Patent number: 9041006Abstract: A silicon carbide MOS semiconductor device is disclosed which suppresses degradation of efficiency percentage yield with respect to a breakdown voltage even when a surface region with a high impurity concentration is formed by ion implantation with such a high dose as required for attaining a good ohmic contact.Type: GrantFiled: March 24, 2009Date of Patent: May 26, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shun-ichi Nakamura, Yoshiyuki Yonezawa, Masahide Gotoh
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Patent number: 8802546Abstract: Gas containing Si, gas containing C and gas containing Cl are introduced into a reacting furnace. SiC epitaxial film is grown on the surface of a 4H—SiC substrate by CVD in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas. The amount of the gas containing Cl relative to the gas containing Si in the gas atmosphere is reduced gradually. At the start of growth, the number of Cl atoms in the gas containing Cl is three times as large as the number of Si atoms in the gas containing Si. The number of Cl atoms in the gas containing Cl relative to the number of Si atoms in the gas containing Si in the gas atmosphere is reduced at a rate of 0.5%/min to 1.0%/min. The method grows silicon carbide semiconductor film at a high rate.Type: GrantFiled: July 16, 2013Date of Patent: August 12, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa
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Publication number: 20140065800Abstract: Gas containing Si, gas containing C and gas containing Cl are introduced into a reacting furnace. SiC epitaxial film is grown on the surface of a 4H—SiC substrate by CVD in a gas atmosphere including raw material gas, additive gas, doping gas and carrier gas. The amount of the gas containing Cl relative to the gas containing Si in the gas atmosphere is reduced gradually. At the start of growth, the number of Cl atoms in the gas containing Cl is three times as large as the number of Si atoms in the gas containing Si. The number of Cl atoms in the gas containing Cl relative to the number of Si atoms in the gas containing Si in the gas atmosphere is reduced at a rate of 0.5%/min to 1.0%/min. The method grows silicon carbide semiconductor film at a high rate.Type: ApplicationFiled: July 16, 2013Publication date: March 6, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasuyuki KAWADA, Yoshiyuki YONEZAWA
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Patent number: 8324631Abstract: A SiC semiconductor substrate is disclosed which includes a SiC single crystal substrate, a nitrogen (N)-doped n-type SiC epitaxial layer in which nitrogen (N) is doped and a phosphorus (P)-doped n-type SiC epitaxial layer in which phosphorus (P) is doped. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are laminated on the silicon carbide single crystal substrate sequentially. The nitrogen (N)-doped n-type SiC epitaxial layer and the phosphorus (P)-doped n-type SiC epitaxial layer are formed by using two or more different dopants, for example, nitrogen and phosphorus, at the time of epitaxial growth. Basal plane dislocations in a SiC device can be reduced.Type: GrantFiled: October 2, 2007Date of Patent: December 4, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Yoshiyuki Yonezawa, Takeshi Tawara
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Publication number: 20120237428Abstract: A method is disclosed with provides stable growth of SiC single crystals, particularly 4H—SiC single crystals, with an effective crystal growth rate for a prolonged time even at a low temperature range of 2000° C. or lower. A raw material containing Si, Ti and Ni is charged into a crucible made of graphite and heat-melted to obtain a solvent. At the same time, C is dissolved out from the crucible into the solvent to obtain a melt. A SiC seed crystal substrate is then brought into contact with the melt such that SiC is supersaturated in the melt in the vicinity of the surface of the SiC seed crystal substrate, thereby allowing growth and production of an SiC single crystal on the SiC seed crystal substrate.Type: ApplicationFiled: March 23, 2012Publication date: September 20, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Mina RYO, Yoshiyuki YONEZAWA, Takeshi SUZUKI