Patents by Inventor Yoshizumi Haraguchi
Yoshizumi Haraguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7986170Abstract: Noise is more effectively reduced in one circuit. When sampling and holding is performed, switching of an ON resistance of MOS transistors (MSH1 and MSH2) that are for sampling is made in two or more stages according to speed of sampling. Here, a level adjustment circuit (20) is provided that generates sample-and-hold pulse signals (?SH1S and ?SH2S), which vary voltage to enable switching the ON resistance of the MOS transistors (MSH1 and MSH2), to be provided to gates of the MOS transistors (MSH1 and MSH2).Type: GrantFiled: March 19, 2009Date of Patent: July 26, 2011Assignee: Renesas Electronics CorporationInventor: Yoshizumi Haraguchi
-
Publication number: 20100265376Abstract: A line sensor includes a second conductive type semiconductor substrate where a first conductive type well region is formed, a pixel line formed in the well region, a plurality of pixels being formed on the well region, the plurality of pixels generating charges corresponding to an incident light, a CCD register unit formed on the well region, a transfer electrode being arranged on the well region, the transfer electrode transferring the charges in response to a transfer clock, an output circuit which outputs a voltage signal corresponding to the charges transferred by the transfer electrode, a wiring part which supplies a reference potential to the well region and the output circuit, and a resistor which is included in a wiring, the wiring connecting a first contact between the well region and the wiring part to a second contact between the output circuit and the wiring part.Type: ApplicationFiled: March 22, 2010Publication date: October 21, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: YOSHIZUMI HARAGUCHI
-
Patent number: 7719037Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.Type: GrantFiled: May 31, 2007Date of Patent: May 18, 2010Assignee: NEC Electronics CorporationInventor: Yoshizumi Haraguchi
-
Publication number: 20090237120Abstract: Noise is more effectively reduced in one circuit. When sampling and holding is performed, switching of an ON resistance of MOS transistors (MSH1 and MSH2) that are for sampling is made in two or more stages according to speed of sampling. Here, a level adjustment circuit (20) is provided that generates sample-and-hold pulse signals (?SH1S and ?SH2S), which vary voltage to enable switching the ON resistance of the MOS transistors (MSH1 and MSH2), to be provided to gates of the MOS transistors (MSH1 and MSH2).Type: ApplicationFiled: March 19, 2009Publication date: September 24, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Yoshizumi HARAGUCHI
-
Patent number: 7403037Abstract: The signal amplifier has a source follower receiving an input signal, a voltage divider generating a bias voltage which is input to the source follower through a different path from the input signal, and an inverter connected in series in the subsequent stage of the source follower and having such characteristics as to compensate characteristics variation of the voltage divider due to manufacturing parameter.Type: GrantFiled: April 29, 2005Date of Patent: July 22, 2008Assignee: NEC Electronics CorporationInventor: Yoshizumi Haraguchi
-
Publication number: 20070278537Abstract: An image sensor includes a reset transistor, reset gate electrodes and a potential shift circuit. The reset transistor includes a reset gate and a reset drain, and resets charges detected by a charge detection device. The reset gate electrodes control a potential of the reset gate. The potential shift circuit initializes output signals in response to a shift pulse, and outputs the output signals to the reset gate electrodes in response to a reset pulse.Type: ApplicationFiled: May 31, 2007Publication date: December 6, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Yoshizumi Haraguchi
-
Publication number: 20050242839Abstract: The signal amplifier has a source follower receiving an input signal, a voltage divider generating a bias voltage which is input to the source follower through a different path from the input signal, and an inverter connected in series in the subsequent stage of the source follower and having such characteristics as to compensate characteristics variation of the voltage divider due to manufacturing parameter.Type: ApplicationFiled: April 29, 2005Publication date: November 3, 2005Applicant: NEC ELECTRONICS CORPORATIONInventor: Yoshizumi Haraguchi
-
Patent number: 6862041Abstract: A circuit for processing charge detecting signals transferred to a floating diffusion amplifier from a charge coupled device includes a first node connected to the floating diffusion amplifier; a first enhancement type FET connected in series between a first fixed-voltage supply line for supplying a first fixed voltage and an output terminal, where the first enhancement type FET has a first gate connected to the first node; and a second enhancement type FET connected in series between a second fixed-voltage supply line for supplying a second fixed voltage and the output terminal, where the second enhancement type FET has a second gate supplied with a third fixed voltage which is different in potential from the second fixed voltage.Type: GrantFiled: January 25, 2001Date of Patent: March 1, 2005Assignee: NEC Electronics CorporationInventor: Yoshizumi Haraguchi
-
Publication number: 20010050714Abstract: The first present invention provides a circuit for processing charge detecting signal transferred to a floating diffusion amplifier from a charge coupled device. The circuit comprises: a first node connected to the floating diffusion amplifier; a first enhancement type field effect transistor being connected in series between a first fixed-voltage supply line for supplying a first fixed voltage and an output terminal, and the first enhancement type field effect transistor having a first gate connected to the first node; and a second enhancement type field effect transistor being connected in series between a second fixed-voltage supply line for supplying a second fixed voltage and the output terminal, wherein the second enhancement type field effect transistor has a second gate supplied with a third fixed voltage which is different in potential from the second fixed voltage.Type: ApplicationFiled: January 25, 2001Publication date: December 13, 2001Applicant: NEC CORPORATIONInventor: Yoshizumi Haraguchi