Patents by Inventor Yoshizumi Sato

Yoshizumi Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7526859
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: May 5, 2009
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Publication number: 20070044294
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Application
    Filed: October 13, 2006
    Publication date: March 1, 2007
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 7134193
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: November 14, 2006
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Publication number: 20050115068
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 2, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 6865801
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: March 15, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 6534873
    Abstract: A ground pattern (12) and power supply pattern (13) which are formed on the surface of a printed wiring board (10) are connected to a ground layer (21) and power supply layer (22) formed as the internal layers via bumps (24a, 24b). The ground pattern (12) need not be connected to the ground layer (21) by uniformly plating the inner side surface of a cavity (43), contributing to an increase in yield and a decrease in cost. When a power supply pattern (13) is to be connected to a power supply layer (22) using through holes, the power supply pattern (13) must be spaced apart from signal pins (14) detouring the region where the through holes are to be formed. However, the distance between the power supply pattern and the signal pins can.be reduced by using bumps. The distance between a semiconductor chip (41) and the signal pins (14) can be reduced to improve the electrical characteristics.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: March 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshizumi Sato, Kenji Sasaoka
  • Patent number: 6507995
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: January 21, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Publication number: 20020046880
    Abstract: A first via land of a wiring layer on a first surface of a first insulation layer that is a rigid layer and a second via land of a wiring layer on a second surface of a second insulation layer that is a flexible layer are electrically and mechanically connected with a conductive pillar pierced through a third insulation layer disposed between the first insulation layer and the second insulation layer. In such a structure, a wiring board that can mount a highly integrated semiconductor device, that is small and thin, and that has high reliability can be accomplished.
    Type: Application
    Filed: October 23, 2001
    Publication date: April 25, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Yoshizumi Sato, Tomitsugu Kojima, Go Takeda
  • Patent number: 6329610
    Abstract: A first via land of a wiring layer on a first surface of a first insulation layer that is a rigid layer and a second via land of a wiring layer on a second surface of a second insulation layer that is a flexible layer are electrically and mechanically connected with a conductive pillar pierced through a third insulation layer disposed between the first insulation layer and the second insulation layer. In such a structure, a wiring board that can mount a highly integrated semiconductor device, that is small and thin, and that has high reliability can be accomplished.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: December 11, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Yoshizumi Sato, Tomitsugu Kojima, Go Takeda
  • Publication number: 20010039720
    Abstract: The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.
    Type: Application
    Filed: July 5, 2001
    Publication date: November 15, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji Sasaoka, Fumitoshi Ikegaya, Takahiro Mori, Tomohisa Motomura, Yoshizumi Sato, Koichiro Shibayama
  • Patent number: 5865934
    Abstract: There is provided a method for arranging conductive bumps at predetermined positions penetrated through an insulating layer during a press integration stage to ensure electrical and thermal conductivities between a wiring pattern and a conductive metal as well as electrical connections between the wiring patterns. More specifically, the sharp tip of the conductive bump is subjected to plastic deformation to form the interconnections between the wiring patterns or between the wiring pattern and the conductive metal. Also provided is a method of manufacturing a printed wiring board. A synthetic resin sheet is sandwiched by the surface on which conductive bumps are formed into a laminate. The laminate is heated until the resin component of the synthetic resin sheet being is in a plastic state or up to a temperature not lower than the grass transition temperature of that resin. At that time, the conductive bumps are forced against the synthetic resin sheet and are penetrated therethrough.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamamoto, Yoshizumi Sato, Tomohisa Motomura, Hiroshi Hamano, Yasushi Arai
  • Patent number: 5736681
    Abstract: There are provided conductive bumps arranged at predetermined positions penetrated through an insulating layer during a press integration stage to ensure electrical and thermal conductivities between a wiring pattern and a conductive metal as well as electrical connections between the wiring patterns. More specifically, the sharp tip of the conductive bump is subjected to plastic deformation to form the interconnections between the wiring patterns or between the wiring pattern and the conductive metal. Also provided is a method of manufacturing a printed wiring board. A synthetic resin sheet is sandwiched by the surface on which conductive bumps are formed into a laminate. The laminate is heated until the resin component of the synthetic resin sheet in a plastic state or up to a temperature not lower than the glass transition temperature of that resin. At that time, the conductive bumps are forced against the synthetic resin sheet and are penetrated therethrough.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: April 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamamoto, Yoshizumi Sato, Tomohisa Motomura, Hiroshi Hamano, Yasushi Arai
  • Patent number: 5407557
    Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: April 18, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Iida, Hiroshi Odaira, Yoshizumi Sato, Yuichi Yamamoto
  • Patent number: 5333379
    Abstract: Small projections are arranged on a molding surface of at least one of an upper die half and a lower die half constituting a molding die, and a predetermined number of conductor circuits each including small projections are formed on the molding surface by electrically plating. A predetermined number of conductor circuits are formed on the molding surface of other die half in the same manner. Subsequently, the molding surfaces of both the die halves are brought in pressure contact with each other so that the electrically plated layers each including small projections on the molding surface are connected electrically. Thereafter, the hollow space between both the die halves is filled with a predetermined resin, whereby the conductor circuits are reversely secured to the resultant molded product to complete production of a three-dimensional wiring board. After electronic components are assembled on the three-dimensional wiring board, the resin is removed from the molded product by dissolving the resin.
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: August 2, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Odaira, Yoshizumi Sato
  • Patent number: 5310966
    Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: May 10, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Iida, Hiroshi Odaira, Yoshizumi Sato, Yuichi Yamamoto