Patents by Inventor Yositake HAYASHI

Yositake HAYASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TEST MARK STRUCTURE, SUBSTRATE SHEET LAMINATE, MULTILAYERED CIRCUIT SUBSTRATE, METHOD FOR INSPECTING LAMINATION MATCHING PRECISION OF MULTILAYERED CIRCUIT SUBSTRATE, AND METHOD FOR DESIGNING SUBSTRATE SHEET LAMINATE
    Publication number: 20080186045
    Abstract: An inspection mark structure has an inspection via hole, which is provided in substrate sheets to be heat-pressed constituting at least two layers of laminates; a round pattern electrode, which is formed on one main face side of the substrate sheet provided with the inspection via hole, and provided around the end face of the inspection via hole at such a predetermined distance as not to come into contact with the end face; and a conduction electrode, which is formed on the other main face side of the substrate sheet provided with the inspection via hole, and provided so as to be electrically connected with the end face of the inspection via hole.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 7, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoji UEDA, Tsukasa SHIRAISHI, Yositake HAYASHI, Rikiya OKIMOTO