Patents by Inventor Yossi Neeman

Yossi Neeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11792325
    Abstract: A computerized-method for a personalized screen recording in a contact center is provided herein. The computerized-method includes, before each interaction between an agent and a customer, operating a predictive screen recording module to yield an Agent Recording Percentage (ARP) value; and based on the ARP value, operating a recording of screen events module for recording one or more voice or digital interactions, on one or more screens associated to a computing device of the agent.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: October 17, 2023
    Assignee: NICE LTD.
    Inventors: Ofir Mecayten, Yaron Cohen, Yossi Neeman
  • Publication number: 20230179712
    Abstract: A computerized-method for a personalized screen recording in a contact center is provided herein. The computerized-method includes, before each interaction between an agent and a customer, operating a predictive screen recording module to yield an Agent Recording Percentage (ARP) value; and based on the ARP value, operating a recording of screen events module for recording one or more voice or digital interactions, on one or more screens associated to a computing device of the agent.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Ofir Mecayten, Yaron Cohen, Yossi Neeman
  • Patent number: 9792399
    Abstract: An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. The block coupling reconfiguration unit is arranged to identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, and to provide the block with an additional terminal capable of providing the same function as the terminal. The block coupling reconfiguration unit is also arranged to replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: October 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Asher Berkovitz, Inbar Ben-Porat, Yossy Neeman
  • Publication number: 20150339427
    Abstract: An integrated circuit hierarchical design tool apparatus comprises a processor arranged to support a block coupling reconfiguration unit. The block coupling reconfiguration unit is capable of receiving block layout data comprising block placement, terminal location data and intra-block connectivity data. The block coupling reconfiguration unit is arranged to identify from the block layout data a block placement level block having a terminal respectively coupled to a plurality of other block placement level blocks by a plurality of nets, and to provide the block with an additional terminal capable of providing the same function as the terminal. The block coupling reconfiguration unit is also arranged to replace a net of the plurality of nets that is coupled to the terminal with a replacement net coupled to the additional terminal.
    Type: Application
    Filed: January 7, 2013
    Publication date: November 26, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Asher BERKOVITZ, Inbar BEN-PORAT, Yossy NEEMAN
  • Publication number: 20140122518
    Abstract: Systems, methods, and machine-readable and executable instructions are provided for codeless array validation. Codeless array validation can include selecting a number of operations associated with processing organizational data, where each of the number of operations includes a number of input schemas and a number of output schemas. Codeless array validation can include constructing a number of rules including the number of input schemas and the number of output schemas. Codeless array validation can include querying a web service, receiving an array response for the organizational data from the web service, and validating the array response codelessly by checking the number of rules against each of a number of data elements comprising the array response.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Yochay Alufer, Yossi Neeman
  • Patent number: 8078781
    Abstract: A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: December 13, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ori Goren, Yaron Netanel, Aviel Livay, Gil Moran, Yossy Neeman
  • Publication number: 20100325481
    Abstract: A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal.
    Type: Application
    Filed: October 20, 2006
    Publication date: December 23, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Odi Dahan, Ori Goren, Yossy Neeman
  • Publication number: 20100199010
    Abstract: A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests.
    Type: Application
    Filed: August 23, 2006
    Publication date: August 5, 2010
    Inventors: Ori Goren, Yaron Netanel, Aviel Livay, Gil Moran, Yossy Neeman