Patents by Inventor Yossi Smeloy
Yossi Smeloy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230139439Abstract: A cryptocurrency miner includes a power supply, a network interface, a compute module, and a controller. The compute module includes compute engine stories coupled in series with the power supply. Each compute engine story includes compute engines coupled in parallel between a voltage input node and voltage output node of the respective compute engine story. The controller receives, via the network interface, a job from a pool server of a mining pool and distributes aspects of the job to the compute engine stories.Type: ApplicationFiled: November 1, 2021Publication date: May 4, 2023Inventors: Yossi Smeloy, Gil Shefer, Eyal Frost, Rony Gutierrez
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Publication number: 20230095559Abstract: A cryptocurrency miner includes a control power supply, a compute power supply, a compute module, and a controller. The compute module includes control circuitry powered based on first power supplied by the control power supply and a compute engine powered based on second power supplied by the compute power supply. The controller causes the control power supply to apply the first power to the control circuitry. The controller further causes the compute power supply to apply the second power to the compute engine after initialization of the control circuitry.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Yossi Smeloy, Gil Shefer, Rony Gutierrez
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Patent number: 9935048Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.Type: GrantFiled: January 10, 2017Date of Patent: April 3, 2018Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yossi Smeloy, Eyal Frost
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Publication number: 20170117220Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.Type: ApplicationFiled: January 10, 2017Publication date: April 27, 2017Inventors: Yossi Smeloy, Eyal Frost
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Patent number: 9577024Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.Type: GrantFiled: February 5, 2014Date of Patent: February 21, 2017Assignee: Mellanox Technologies Ltd.Inventors: Yossi Smeloy, Eyal Frost
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Patent number: 9111602Abstract: A system and method for accurately distributing a master reference voltage to a plurality of local circuits within a system. A central master reference voltage is distributed to a plurality of local circuits as a difference in the voltage of a pair of conductors oriented substantially spatially parallel. Local reference voltages are generated based on the master reference voltage and a local voltage source.Type: GrantFiled: March 18, 2010Date of Patent: August 18, 2015Assignee: MELLANOX TECHNOLOGIES, LTD.Inventor: Yossi Smeloy
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Patent number: 9088368Abstract: Methods and devices for laser driver calibration are disclosed. The methods and devices disclose determining first and second bit error rates for use in calibrating the laser driver. The methods and devices also disclose that if the first bit error rate associated with a first initial value is above a predetermined bit error rate, increasing the first initial value until the first bit error rate is not above the predetermined bit error rate, and if the second bit error rate associated with a second initial value is above a predetermined bit error rate, decreasing the second initial value until the second bit error rate is not above the predetermined bit error rate. In addition, the methods and devices disclose setting a calibrated parameter for the laser driver based, at least in part, on the increased first initial value and the decreased second initial value.Type: GrantFiled: January 3, 2013Date of Patent: July 21, 2015Assignee: Mellanox Technologies, Ltd.Inventors: Ihab Khoury, Yossi Smeloy
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Publication number: 20140231956Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.Type: ApplicationFiled: February 5, 2014Publication date: August 21, 2014Applicant: Mellanox Technologies Ltd.Inventors: Yossi Smeloy, Eyal Frost
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Publication number: 20140186029Abstract: Methods and devices for laser driver calibration are disclosed. The methods and devices disclose determining first and second bit error rates for use in calibrating the laser driver. The methods and devices also disclose that if the first bit error rate associated with a first initial value is above a predetermined bit error rate, increasing the first initial value until the first bit error rate is not above the predetermined bit error rate, and if the second bit error rate associated with a second initial value is above a predetermined bit error rate, decreasing the second initial value until the second bit error rate is not above the predetermined bit error rate. In addition, the methods and devices disclose setting a calibrated parameter for the laser driver based, at least in part, on the increased first initial value and the decreased second initial value.Type: ApplicationFiled: January 3, 2013Publication date: July 3, 2014Applicant: MELLANOX TECHNOLOGIES, LTD.Inventors: Ihab Khoury, Yossi Smeloy
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Publication number: 20100188140Abstract: A system and method for accurately distributing a master reference voltage to a plurality of local circuits within a system. A central master reference voltage is distributed to a plurality of local circuits as a difference in the voltage of a pair of conductors oriented substantially spatially parallel. Local reference voltages are generated based on the master reference voltage and a local voltage source.Type: ApplicationFiled: March 18, 2010Publication date: July 29, 2010Applicant: MELLANOX TECHNOLOGIES LTD.Inventor: Yossi SMELOY
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Publication number: 20090302923Abstract: A system and method for compensation of offset voltage in a digital differential input buffer driven by a terminated transmission line. Offset compensation currents are injected at the output of the first stage of the input buffer, which has a higher impedance than the terminated transmission line at the input of the buffer. The compensation current is determined by a network of MOS transistors, which saves die space compared to resistors. A pair of voltage multiplexers provides for compensation currents to correct offsets of either polarity. Offset correction currents are determined anew each time the system is powered up, compensating for component aging. The offset correction can also be performed while the input buffer is operating, during periods when the input is quiescent, and/or by adjusting the offset correction according to the duty cycle of the detected input.Type: ApplicationFiled: March 1, 2009Publication date: December 10, 2009Applicant: Mellanox Technologies Ltd.Inventors: Yossi Smeloy, Ronen Eckhouse
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Publication number: 20070258546Abstract: A system and method for compensation of offset voltage in a digital differential input buffer driven by a terminated transmission line. Offset compensation currents are injected at the output of the first stage of the input buffer, which has a higher impedance than the terminated transmission line at the input of the buffer. The compensation current is determined by a network of MOS transistors, which saves die space compared to resistors. A pair of voltage multiplexers provides for compensation currents to correct offsets of either polarity. Offset correction currents are determined anew each time the system is powered up, compensating for component aging. The offset correction can also be performed while the input buffer is operating, during periods when the input is quiescent, and/or by adjusting the offset correction according to the duty cycle of the detected input.Type: ApplicationFiled: May 7, 2007Publication date: November 8, 2007Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Yossi Smeloy, Ronen Eckhouse
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Publication number: 20070236275Abstract: A system and method for distributing a reference voltage in a system such as an integrated circuit wherein a master reference voltage is distributed via a differential pair of conductors Local reference voltage generators produce local reference voltages proportional to the master reference voltage, but referred to local ground and/or a local power supply voltage.Type: ApplicationFiled: March 27, 2007Publication date: October 11, 2007Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Yossi Smeloy, Ronen Eckhouse
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Publication number: 20070228410Abstract: A system for protecting a high-speed input/output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input/output pad and a trigger input. The anode and the trigger input form a reverse-biased junction that, during normal operation of the integrated circuit, isolates the triggering mechanism from the input/output pad when power is applied to the integrated circuit.Type: ApplicationFiled: March 27, 2007Publication date: October 4, 2007Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Yossi Smeloy, Ronen Eckhouse, Eyal Frost