Patents by Inventor Yosuke Kanzaki

Yosuke Kanzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9349750
    Abstract: A semiconductor device includes: a transistor including a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, and a source electrode and a drain electrode over the semiconductor layer; a first insulating film comprising an inorganic material over the transistor; a second insulating film comprising an organic material over the first insulating film; a first conductive film over the second insulating film and in a region overlapping with the semiconductor layer; a third insulating film comprising an inorganic material over the first conductive film; and a second conductive film over the third insulating film and in a region overlapping with the first conductive film. The absolute value of a first potential applied to the first conductive film is greater than the absolute value of a second potential applied to the second conductive film.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: May 24, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Miyake, Shunpei Yamazaki, Yoshifumi Tanada, Manabu Sato, Toshinari Sasaki, Kenichi Okazaki, Junichi Koezuka, Takuya Matsuo, Hiroshi Matsukizono, Yosuke Kanzaki, Shigeyasu Mori
  • Patent number: 9331207
    Abstract: A semiconductor device includes a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film in contact with the gate insulating film and including a channel formation region which overlaps with the gate electrode; a source electrode and a drain electrode over the oxide semiconductor film; and an oxide insulating film over the oxide semiconductor film, the source electrode, and the drain electrode. The source electrode and the drain electrode each include a first metal film having an end portion at the end of the channel formation region, a second metal film over the first metal film and containing copper, and a third metal film over the second metal film. The second metal film is formed on the inner side than the end portion of the first metal film.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 3, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Shunpei Yamazaki, Naoya Sakamoto, Takahiro Sato, Shunsuke Koshioka, Takayuki Cho, Yoshitaka Yamamoto, Takuya Matsuo, Hiroshi Matsukizono, Yosuke Kanzaki
  • Patent number: 9312278
    Abstract: To improve the reliability of a transistor as well as to inhibit fluctuation in electric characteristics. A display device includes a pixel portion and a driver circuit portion outside the pixel portion; the pixel portion includes a pixel transistor, a first insulating film covering the pixel transistor and including an inorganic material, a second insulating film including an organic material over the first insulating film, and a third insulating film including an inorganic material over the second insulating film; and the driver circuit portion includes a driving transistor to supply a signal to the pixel transistor, the first insulating film covering the driving transistor, and the second insulating film over the first insulating film, and further includes a region in which the third insulating film is not formed over the second insulating film or a region in which the second insulating film is not covered with the third insulating film.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 12, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Junichi Koezuka, Yukinori Shima, Yasuharu Hosaka, Kenichi Okazaki, Takuya Matsuo, Shigeyasu Mori, Yosuke Kanzaki, Hiroshi Matsukizono
  • Patent number: 8884297
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 11, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Publication number: 20140306218
    Abstract: Variation in the electrical characteristics of transistors is minimized and reliability of the transistors is improved. A display device includes a pixel portion 104 and a driver circuit portion 106 outside the pixel portion. The pixel portion includes a pixel transistor, a first insulating layer 122 which covers the pixel transistor and includes an inorganic material, a second insulating layer 124 which is over the first insulating layer and includes an organic material, and a third insulating layer 128 which is over the second insulating layer and includes an inorganic material. The driver circuit portion includes a driving transistor for supplying a signal to the pixel transistor, and the first insulating layer covering the driving transistor. The second insulating layer is not formed in the driver circuit portion.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 16, 2014
    Inventors: Junichi KOEZUKA, Masahiro KATAYAMA, Yukinori SHIMA, Kenichi OKAZAKI, Takuya MATSUO, Shigeyasu MORI, Yosuke KANZAKI, Hiroshi MATSUKIZONO
  • Publication number: 20140306220
    Abstract: To provide a novel semiconductor device in which a reduction in channel length is controlled. The semiconductor device includes an oxide semiconductor layer having a crystal part, and a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a channel formation region and an n-type region in contact with the source electrode layer or the drain electrode layer. The crystal orientation of the crystal part is different between the channel formation region and the n-type region.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 16, 2014
    Inventors: Junichi KOEZUKA, Kenichi OKAZAKI, Masahiro TAKAHASHI, Takuya MATSUO, Shigeyasu MORI, Yosuke KANZAKI, Hiroshi MATSUKIZONO
  • Patent number: 8853697
    Abstract: To inhibit a metal element contained in a glass substrate from being diffused into a gate insulating film or an oxide semiconductor film. A semiconductor device includes a glass substrate, a base insulating film formed using metal oxide over the glass substrate, a gate electrode formed over the base insulating film, a gate insulating film formed over the gate electrode, an oxide semiconductor film which is formed over the gate insulating film and overlapping with the gate electrode, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In a region of the base insulating film that is present in a range of 3 nm or less from a surface of the base insulating film, the concentration of a metal element contained in the glass substrate is less than or equal to 1×1018 atoms/cm3.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 7, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kenichi Okazaki, Takuya Matsuo, Yoshitaka Yamamoto, Hiroshi Matsukizono, Yosuke Kanzaki
  • Patent number: 8785926
    Abstract: The semiconductor conductor device includes a gate electrode 106, an oxide semiconductor film 110, a source electrode 114a and a drain electrode 114b, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface 214a of the source electrode and a second side surface 214b of the drain electrode opposite to the first side surface 214a. The oxide semiconductor film has a side surface which overlaps with the gate electrode, which has a first high resistance region positioned between a first region 206a that is the nearest to one end 314a of the first side surface 214a and a second region 206b that is the nearest to one end 314b of the second side surface 214b. The first high resistance region has a corrugated side surface or the like.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 22, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Masatoshi Yokoyama, Tsutomu Murakawa, Kenichi Okazaki, Masayuki Sakakura, Takuya Matsuo, Yosuke Kanzaki, Hiroshi Matsukizono, Yoshitaka Yamamoto
  • Publication number: 20140139775
    Abstract: A semiconductor device includes: a transistor including a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, and a source electrode and a drain electrode over the semiconductor layer; a first insulating film comprising an inorganic material over the transistor; a second insulating film comprising an organic material over the first insulating film; a first conductive film over the second insulating film and in a region overlapping with the semiconductor layer; a third insulating film comprising an inorganic material over the first conductive film; and a second conductive film over the third insulating film and in a region overlapping with the first conductive film. The absolute value of a first potential applied to the first conductive film is greater than the absolute value of a second potential applied to the second conductive film.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 22, 2014
    Inventors: Hiroyuki MIYAKE, Shunpei YAMAZAKI, Yoshifumi TANADA, Manabu SATO, Toshinari SASAKI, Kenichi OKAZAKI, Junichi KOEZUKA, Takuya MATSUO, Hiroshi MATSUKIZONO, Yosuke KANZAKI, Shigeyasu MORI
  • Publication number: 20140117350
    Abstract: To improve the reliability of a transistor as well as to inhibit fluctuation in electric characteristics. A display device includes a pixel portion and a driver circuit portion outside the pixel portion; the pixel portion includes a pixel transistor, a first insulating film covering the pixel transistor and including an inorganic material, a second insulating film including an organic material over the first insulating film, and a third insulating film including an inorganic material over the second insulating film; and the driver circuit portion includes a driving transistor to supply a signal to the pixel transistor, the first insulating film covering the driving transistor, and the second insulating film over the first insulating film, and further includes a region in which the third insulating film is not formed over the second insulating film or a region in which the second insulating film is not covered with the third insulating film.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 1, 2014
    Inventors: Junichi KOEZUKA, Yukinori SHIMA, Yasuharu HOSAKA, Kenichi OKAZAKI, Takuya MATSUO, Shigeyasu MORI, Yosuke KANZAKI, Hiroshi MATSUKIZONO
  • Publication number: 20140021466
    Abstract: A semiconductor device includes a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film in contact with the gate insulating film and including a channel formation region which overlaps with the gate electrode; a source electrode and a drain electrode over the oxide semiconductor film; and an oxide insulating film over the oxide semiconductor film, the source electrode, and the drain electrode. The source electrode and the drain electrode each include a first metal film having an end portion at the end of the channel formation region, a second metal film over the first metal film and containing copper, and a third metal film over the second metal film. The second metal film is formed on the inner side than the end portion of the first metal film.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 23, 2014
    Inventors: Shunpei YAMAZAKI, Naoya SAKAMOTO, Takahiro SATO, Shunsuke KOSHIOKA, Takayuki CHO, Yoshitaka YAMAMOTO, Takuya MATSUO, Hiroshi MATSUKIZONO, Yosuke KANZAKI
  • Publication number: 20130270555
    Abstract: An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film. The channel length L of the oxide semiconductor film is more than or equal to 1 ?m and less than or equal to 50 ?m. The oxide semiconductor film has a peak at a rotation angle 2? in the vicinity of 31° in X-ray diffraction measurement.
    Type: Application
    Filed: April 12, 2013
    Publication date: October 17, 2013
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kenichi Okazaki, Masatoshi Yokoyama, Masayuki Sakakura, Yukinori Shima, Yosuke Kanzaki, Hiroshi Matsukizono, Takuya Matsuo, Yoshitaka Yamamoto
  • Publication number: 20130270554
    Abstract: The semiconductor conductor device includes a gate electrode 106, an oxide semiconductor film 110, a source electrode 114a and a drain electrode 114b, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface 214a of the source electrode and a second side surface 214b of the drain electrode opposite to the first side surface 214a. The oxide semiconductor film has a side surface which overlaps with the gate electrode, which has a first high resistance region positioned between a first region 206a that is the nearest to one end 314a of the first side surface 214a and a second region 206b that is the nearest to one end 314b of the second side surface 214b. The first high resistance region has a corrugated side surface or the like.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 17, 2013
    Inventors: Masatoshi YOKOYAMA, Tsutomu MURAKAWA, Kenichi OKAZAKI, Masayuki SAKAKURA, Takuya MATSUO, Yosuke KANZAKI, Hiroshi MATSUKIZONO, Yoshitaka YAMAMOTO
  • Publication number: 20130228774
    Abstract: To inhibit a metal element contained in a glass substrate from being diffused into a gate insulating film or an oxide semiconductor film. A semiconductor device includes a glass substrate, a base insulating film formed using metal oxide over the glass substrate, a gate electrode formed over the base insulating film, a gate insulating film formed over the gate electrode, an oxide semiconductor film which is formed over the gate insulating film and overlapping with the gate electrode, and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In a region of the base insulating film that is present in a range of 3 nm or less from a surface of the base insulating film, the concentration of a metal element contained in the glass substrate is less than or equal to 1×1018 atoms/cm3.
    Type: Application
    Filed: February 26, 2013
    Publication date: September 5, 2013
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kenichi OKAZAKI, Takuya MATSUO, Yoshitaka YAMAMOTO, Hiroshi MATSUKIZONO, Yosuke KANZAKI
  • Patent number: 8440548
    Abstract: An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a microcrystalline silicon film or an amorphous silicon film having a thickness that allows the microcrystalline silicon film or the amorphous silicon film to be completely oxidized by later plasma oxidation (e.g., a thickness greater than 0 nm and less than or equal to 5 nm) is formed.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: May 14, 2013
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hidekazu Miyairi, Takashi Ienaga, Masao Moriguchi, Yosuke Kanzaki
  • Patent number: 8436353
    Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 7, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Tokuo Yoshida, Yuhichi Saitoh, Yasuaki Iwase, Yosuke Kanzaki, Mayuko Sakamoto
  • Publication number: 20130056742
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Application
    Filed: May 6, 2011
    Publication date: March 7, 2013
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Publication number: 20120034765
    Abstract: An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a microcrystalline silicon film or an amorphous silicon film having a thickness that allows the microcrystalline silicon film or the amorphous silicon film to be completely oxidized by later plasma oxidation (e.g., a thickness greater than 0 nm and less than or equal to 5 nm) is formed.
    Type: Application
    Filed: July 19, 2011
    Publication date: February 9, 2012
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Takashi IENAGA, Masao MORIGUCHI, Yosuke KANZAKI
  • Publication number: 20110147756
    Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.
    Type: Application
    Filed: September 14, 2009
    Publication date: June 23, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masao Moriguchi, Tokuo Yoshida, Yuhichi Saitoh, Yasuaki Iwase, Yosuke Kanzaki, Mayuko Sakamoto