Abstract: Disclosed are a semiconductor device capable of reducing the number of program fuses used therein, and a fuse circuit selection method capable of reducing the number of program fuses. The semiconductor device includes: a fuse circuit (11) and an entire inversion fuse circuit (12), each of which includes plural program fuses, and which store desired addresses based on cutting patterns of the plural program fuses, wherein the fuse circuit (11) and the entire inversion fuse circuit (12) are configured to be capable of storing addresses different from each other based on the same cutting pattern. As described above, since plural types of the cutting patterns of the program fuses exist even in the same address, the fuse circuit for use is appropriately selected, thus it is made possible to reduce the number of fuse elements to be cut as a whole. Thus, manufacturing cost of the semiconductor device can be reduced, and in addition, it is made possible to enhance reliability of the semiconductor device.

Abstract: A prober for a semiconductor wafer test includes a stage, a probe card, and an adjuster The stage has a first region and a second region other than the first region The first region is covered by a wafer on which a plurality of electrode pads is provided. The probe card includes a plurality of probe pins to be in contact with the plurality of electrode pads. The adjuster is included in the stage and adjusts a temperature of the wafer and the second region.

Abstract: A push switch includes a base board disposed in a bottom wall of a switch housing, a switch knob which projects or retracts from the switch housing so as to separate or have contact relative to the base board, a partition for zoning an inside portion of the switching housing into a first switching room and a second switching room, a first light source disposed on the base board and positioned in the first switching room, and a second light source disposed on the base board and positioned in the second switching room, the switch knob including a first translucent path for guiding light from the first light source to a surface, a second translucent path for guiding light from the second light source to a surface, and a non-translucent wall disposed between the first and second translucent paths.

Abstract: A fuse detection method for reading out a program state of each fuse and generating a killer signal indicating the program state of the fuse; counting the program state indicated by the killer signal to obtain a count value; inputting an expected value for the program state of the fuse; and determining whether the count value coincides with the expected value by comparing the count value with the expected value.

Abstract: A probe card for use in testing wafers for semiconductor devices is provided. In the probe card, a region having a plurality of probes corresponding to respective chips is divided into a plurality of subregions. A tester signal is switched between a pair of subregions thus divided so that the tester signal is supplied to one of the pair of subregions. The object to be measured by the probe card is switched according to chip arrangement on the semiconductor wafer by the switching of the tester signal, whereby useless parts in the periphery of the wafer are eliminated and the measurement efficiency is improved.

Abstract: A probe card has a plurality of probe needle groups arranged in a predetermined pattern. The predetermined pattern is obtained by assuming a plurality of unit regions 11-14 arranged adjacent to each other to form a chip group region. The number of unit regions is equal in number to indexes. One of the unit regions included in the chip group regions is defined as a specific unit region. A plurality of the chip group regions are arranged without space therebetween to cover a size of a wafer. The arranged chip group regions form a virtual cover pattern. The arrangement of the specific unit regions is extracted to form the predetermined pattern. Each probe needle group is arranged at the position corresponding to each specific unit region of the predetermined pattern.

Abstract: A fuse detection method according to the present invention includes reading out a program state of each fuse and generating a killer signal indicating the program state of the fuse; counting the program state indicated by the killer signal to obtain a count value; inputting an expected value for the program state of the fuse; and determining whether the count value coincides with the expected value by comparing the count value with the expected value.

Abstract: Disclosed are a semiconductor device capable of reducing the number of program fuses used therein, and a fuse circuit selection method capable of reducing the number of program fuses. The semiconductor device includes: a fuse circuit (11) and an entire inversion fuse circuit (12), each of which includes plural program fuses, and which store desired addresses based on cutting patterns of the plural program fuses, wherein the fuse circuit (11) and the entire inversion fuse circuit (12) are configured to be capable of storing addresses different from each other based on the same cutting pattern. As described above, since plural types of the cutting patterns of the program fuses exist even in the same address, the fuse circuit for use is appropriately selected, thus it is made possible to reduce the number of fuse elements to be cut as a whole. Thus, manufacturing cost of the semiconductor device can be reduced, and in addition, it is made possible to enhance reliability of the semiconductor device.

Abstract: Disclosed are a semiconductor device capable of reducing the number of program fuses used therein, and a fuse circuit selection method. The semiconductor device includes at least one first fuse circuit including: a storage circuit group which stores a desired address based on a cutting pattern of the plural program fuses; a hit detection unit which detects a match between the address stored in the storage circuit group and a selected address; and a use determination unit which activates the hit detection unit in response to the fact that at least one of the program fuses is cut. As described above, the first fuse circuit determines whether the first fuse circuit is in a used state or in an unused state depending on whether or not the program fuse itself is cut. Accordingly, an enable fuse becomes unnecessary.

Abstract: There is provided a memory testing apparatus and a memory testing method, for testing a semiconductor memory having redundant cells. In addition to a plurality of main cell fail information memories for a main cell array in the semiconductor memory under test, one redundant cell fail information memory is provided for redundant cells in the semiconductor memory under test. An address synthesizing circuit receives respective comparison results outputted in parallel from a plurality of comparators, each of which compares an output signal outputted from a semiconductor memory under test with an expected value, and an address supplied to the semiconductor memory under test, and for synthesizing a redundant cell fail information memory address for the redundant cell fail information memory.

Abstract: There is provided a memory testing apparatus and a memory testing method, for testing a semiconductor memory having redundant cells. In addition to a plurality of main cell fail information memories for a main cell array in the semiconductor memory under test, one redundant cell fail information memory is provided for redundant cells in the semiconductor memory under test. An address synthesizing circuit receives respective comparison results outputted in parallel from a plurality of comparators, each of which compares an output signal outputted from a semiconductor memory under test with an expected value, and an address supplied to the semiconductor memory under test, and for synthesizing a redundant cell fail information memory address for the redundant cell fail information memory.