Patents by Inventor Yosuke Kusano
Yosuke Kusano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240149773Abstract: Disclosed is a seat including: sensors which includes a first cushion sensor provided at a seat cushion in a position corresponding to buttocks of an occupant, a second cushion sensor provided at the seat cushion and located farther frontward than the first cushion sensor, a first back sensor provided at a seat back and located in a lower position thereof, and a second back sensor provided at the seat back and located above the first back sensor; and a controller connected to the sensors and thereby allowed to acquire pressure values from the respective sensors. The controller is configured to identify the motion of the occupant based on outputs of at least two sensors of the first cushion sensor, the second cushion sensor, the first back sensor, and the second back sensor.Type: ApplicationFiled: January 9, 2024Publication date: May 9, 2024Inventors: Hiroyuki KAKU, Atsushi KUSANO, Hiroyuki NUMAJIRI, Satoshi FUJITA, Takako MIYOSHI, Munetaka KOWA, Ryuichiro HIROSE, Yoshikazu ITO, Yosuke HIGASHI, Satoshi SUZUKI, Ryosuke SATO, Kento UETAKE, Yasuharu OTSUKA, Satoru KANEDA
-
Patent number: 11932147Abstract: Disclosed is a seat including: sensors which includes a first cushion sensor provided at a seat cushion in a position corresponding to buttocks of an occupant, a second cushion sensor provided at the seat cushion and located farther frontward than the first cushion sensor, a first back sensor provided at a seat back and located in a lower position thereof, and a second back sensor provided at the seat back and located above the first back sensor; and a controller connected to the sensors and thereby allowed to acquire pressure values from the respective sensors. The controller is configured to identify the motion of the occupant based on outputs of at least two sensors of the first cushion sensor, the second cushion sensor, the first back sensor, and the second back sensor.Type: GrantFiled: February 28, 2019Date of Patent: March 19, 2024Assignee: TS TECH CO., LTD.Inventors: Hiroyuki Kaku, Atsushi Kusano, Hiroyuki Numajiri, Satoshi Fujita, Takako Miyoshi, Munetaka Kowa, Ryuichiro Hirose, Yoshikazu Ito, Yosuke Higashi, Satoshi Suzuki, Ryosuke Sato, Kento Uetake, Yasuharu Otsuka, Satoru Kaneda
-
Patent number: 10609317Abstract: A latch unit that starts an operation of capturing a data signal according to a startup instruction signal and holds the data signal and ends the capturing operation at a timing at which an execution instruction signal is input, a first signal path that transfers a latch timing signal as the startup instruction signal, and a second signal path that transfers the latch timing signal as the execution instruction signal are included, and a first logic element that outputs a first output signal switched to a logical value according to a logical value of an input signal at a first predetermined timing, and a signal maintenance logic circuit that continues to output a second output signal with a predetermined logical value according to the logical value of the input signal until initialization of a reset signal is indicated are arranged in the second signal path.Type: GrantFiled: May 3, 2017Date of Patent: March 31, 2020Assignee: OLYMPUS CORPORATIONInventor: Yosuke Kusano
-
Publication number: 20170237928Abstract: A latch unit that starts an operation of capturing a data signal according to a startup instruction signal and holds the data signal and ends the capturing operation at a timing at which an execution instruction signal is input, a first signal path that transfers a latch timing signal as the startup instruction signal, and a second signal path that transfers the latch timing signal as the execution instruction signal are included, and a first logic element that outputs a first output signal switched to a logical value according to a logical value of an input signal at a first predetermined timing, and a signal maintenance logic circuit that continues to output a second output signal with a predetermined logical value according to the logical value of the input signal until initialization of a reset signal is indicated are arranged in the second signal path.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Applicant: OLYMPUS CORPORATIONInventor: Yosuke Kusano
-
Patent number: 9571777Abstract: An analog/digital converter includes: a ramp signal generation circuit that generates a ramp signal; a comparison circuit that compares potential of an input analog signal with potential of the ramp signal and outputs a comparator output signal if the potential of the ramp signal satisfies the predetermined condition; a count control circuit that divides a predetermined ramp period in which the ramp signal generation circuit outputs the ramp signal into a predetermined number n of divided ramp periods and outputs a count-stop signal; a counter circuit that counts time in the divided ramp period and outputs a count value of the counted time; and a decoder circuit that generates a digital signal according to a count value and a digital value corresponding to any one of the divided ramp periods in which the counter circuit has started counting of time and outputs the generated digital signal.Type: GrantFiled: December 14, 2015Date of Patent: February 14, 2017Assignee: OLYMPUS CORPORATIONInventor: Yosuke Kusano
-
Patent number: 9338384Abstract: A solid-state imaging apparatus includes a pixel unit which has a plurality of pixels disposed in a two-dimensional matrix shape, wherein each of the pixels that a photoelectrical conversion element which generates a photoelectrical conversion signal corresponding to an amount of incident light disposed on a first substrate, and which outputs a photoelectrical conversion signal generated by each of the pixels to each row as a pixel signal, and an analog-to-digital converter which is disposed on every one or more columns of the pixel unit and generates a digital signal by digitizing a phase state of a multi-phase clock including clock signals of a plurality of phases different from each other at predetermined fixed intervals according to the pixel signal. Each of first and second circuit configuration units whose circuit scales are determined according to the multi-phase clock is disposed on a different substrate of a first or second substrate.Type: GrantFiled: December 6, 2013Date of Patent: May 10, 2016Assignee: OLYMPUS CORPORATIONInventors: Yosuke Kusano, Susumu Yamazaki
-
Publication number: 20160100115Abstract: An analog/digital converter includes; a ramp signal generation circuit that generates a ramp signal; a comparison circuit that compares potential of an input analog signal with potential of the ramp signal and outputs a comparator output signal if the potential of the ramp signal satisfies the predetermined condition; a count control circuit that divides a predetermined ramp period in which the ramp signal generation circuit outputs the ramp signal into a predetermined number n of divided ramp periods and outputs a count-stop signal; a counter circuit that counts time in the divided ramp period and outputs a count value of the counted time; and a decoder circuit that generates a digital signal according to a count value and a digital value corresponding to any one of the divided ramp periods in which the counter circuit has started counting of time and outputs the generated digital signal.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Applicant: OLYMPUS CORPORATIONInventor: Yosuke Kusano
-
Patent number: 9160318Abstract: A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.Type: GrantFiled: September 18, 2013Date of Patent: October 13, 2015Assignee: OLYMPUS CORPORATIONInventor: Yosuke Kusano
-
Publication number: 20140191112Abstract: A solid-state imaging apparatus includes a pixel unit which has a plurality of pixels disposed in a two-dimensional matrix shape, wherein each of the pixels that a photoelectrical conversion element which generates a photoelectrical conversion signal corresponding to an amount of incident light disposed on a first substrate, and which outputs a photoelectrical conversion signal generated by each of the pixels to each row as a pixel signal, and an analog-to-digital converter which is disposed on every one or more columns of the pixel unit and generates a digital signal by digitizing a phase state of a multi-phase clock including clock signals of a plurality of phases different from each other at predetermined fixed intervals according to the pixel signal. Each of first and second circuit configuration units whose circuit scales are determined according to the multi-phase clock is disposed on a different substrate of a first or second substrate.Type: ApplicationFiled: December 6, 2013Publication date: July 10, 2014Applicant: OLYMPUS CORPORATIONInventors: Yosuke Kusano, Susumu Yamazaki
-
Publication number: 20140084140Abstract: A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.Type: ApplicationFiled: September 18, 2013Publication date: March 27, 2014Applicant: OLYMPUS CORPORATIONInventor: Yosuke Kusano