Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.

Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.

Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.

Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.

Abstract: A memory control device includes a host interface, a memory interface, and a controller configured to control the memory interface to output data to a non-volatile semiconductor memory for writing therein. The data include first data that the host interface received from a host, second data read out from the non-volatile semiconductor memory for memory refresh, and third data read out form the non-volatile semiconductor memory for garbage collection. When the memory refresh is not carried out, the controller adjusts a ratio of the first data with respect to the third data to be a first value. When the memory refresh is carried out, the controller calculates a second value based on the first value, and adjusts a ratio of the first data with respect to a total of the second data and the third data to be the second value.

Abstract: A memory control device includes a host interface, a memory interface, and a controller configured to control the memory interface to output data to a non-volatile semiconductor memory for writing therein. The data include first data that the host interface received from a host, second data read out from the non-volatile semiconductor memory for memory refresh, and third data read out form the non-volatile semiconductor memory for garbage collection. When the memory refresh is not carried out, the controller adjusts a ratio of the first data with respect to the third data to be a first value. When the memory refresh is carried out, the controller calculates a second value based on the first value, and adjusts a ratio of the first data with respect to a total of the second data and the third data to be the second value.

Abstract: According to one embodiment, a write detector detects a predetermined state where a flash memory contains an area to which write data subject to a write request from a host is to be written and from which data has been erased. A data reception controller allows a data buffer to receive the requested write data in accordance with the detection of the predetermined state.