Patents by Inventor Yosuke Mizukawa

Yosuke Mizukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit with layer for isolating elements in substrate
    Patent number: 5578862
    Abstract: By reverse biasing the PN junction formed around a semiconductor element, the semiconductor element is isolated from other elements. The PN junction around the semiconductor element is a junction between a layer surrounding the semiconductor element and a layer disposed outside the layer. Jointly with the layer constituting the semiconductor, the layer surrounding the semiconductor element forms a parasitic diode. The potential of the layer on the semiconductor element to be connected to the layer surrounding the semiconductor element is detected, and based on this potential, the voltage to be applied to the parasitic diode is controlled so as to be constant. When the voltage to be applied to the parasitic diode is lower than a threshold, the parasitic diode will be in a cutoff state.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: November 26, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuo Fujii, Yosuke Mizukawa, Yasuo Mitsuhashi