Patents by Inventor Yosuke Mizutani

Yosuke Mizutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080151676
    Abstract: A semiconductor integrated circuit in which a semiconductor chip 4 having a semiconductor memory and a mother chip 2 having logic circuit are mounted in a single package, wherein the leak current of the semiconductor chip 4 is reduced in standby state. A switch cell 20 that connects to the power pad 10 of the semiconductor chip 4 and that supplies power voltage from the exterior to the semiconductor chip 4 is provided to the mother chip 2. The switch cell 20 cuts off the connection between the power pad 10 of the semiconductor chip 4 and the power voltage line of the semiconductor memory of the mother chip 2 by using a control signal from a control circuit when the semiconductor memory is in standby mode. Leak current generated in the semiconductor memory can thereby be reduced.
    Type: Application
    Filed: December 14, 2007
    Publication date: June 26, 2008
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventor: Yosuke Mizutani
  • Patent number: 5677738
    Abstract: A video signal converter comprising a frequency setting circuit, a first clock generator, a second clock generator, an analog-to-digital converter, a line conversion ratio setting circuit, a number of scanning lines converter, a frame memory, a writing controller, a reading controller and a digital-to-analog converter is disclosed. The frequency setting circuit sets a first frequency Fi which satisfies a formula: Fi.ltoreq.(To.times.Fo)/Ti, where Ti is a horizontal scanning period of a first analog video signal, To is a horizontal scanning period of a second analog video signal and Fo is a second frequency. The line conversion ratio setting circuit sets a line conversion ratio R which satisfies an equation: R=m/k, based on a width-to-height ratio 1/m of each pixel of the first digital video data and a width-to-height ratio 1/k of each pixel of second digital video data.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: October 14, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yosuke Mizutani, Seiya Ota
  • Patent number: 5276714
    Abstract: A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: January 4, 1994
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshihiro Hori, Kazuo Naganawa, Yoshikazu Asano, Yosuke Mizutani, Shuji Yanase
  • Patent number: 4979037
    Abstract: An apparatus (MD) for reproducing, by a low-frequency replacement method, a noise-free high definition video (MUSE) signal obtained by band-compressing the high definition video signal in a time-compressed integration Sub-Nyquist encoding system so as to include no aliasing noise in a low-frequency component below 4 MHz. This reproducing apparatus includes a converter (3) for converting a reproduced or received MUSE signal into digital data and a memory (7) for outputting feedback data in which preceding by two fields and data preceding by four fields with respect to the current field are alternately arranged, a circuit (6; 33) for replacing/non-replacing the data preceding by four fields by first data corresponding to the current field data from the current field data and the feedback data and deriving a data train in which the first data and the data preceding by two fields are alternately arranged.
    Type: Grant
    Filed: April 14, 1989
    Date of Patent: December 18, 1990
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yosuke Mizutani, Takehiko Asano, Syuji Yanase, Shinichiro Kitagawa, Akihiko Yamashita