Patents by Inventor Yosuke Nakata

Yosuke Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240422914
    Abstract: Provided is a technique capable of reducing wiring inductance of a smoothing capacitor. A circuit pattern electrically connected to a semiconductor element is provided on an insulating substrate on a cooler. A smoothing capacitor is disposed not to be overlapped with the semiconductor element in a plan view to include an inner electrode forming capacitance, a capacitor case housing the inner electrode, and a terminal protruding from the capacitor case seamlessly. A first sealing portion covers at least a part of each of the terminal of the smoothing capacitor, the insulating substrate, and the circuit pattern. The terminal of the smoothing capacitor and the circuit pattern are directly connected to each other by bonding force of an interface between the terminal and the circuit pattern.
    Type: Application
    Filed: April 3, 2024
    Publication date: December 19, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke NAKATA, Yuji SATO, Kentaro YOSHIDA, Kei HAYASHI
  • Publication number: 20240402583
    Abstract: A projector includes an exterior housing having a first wall, an introduction port via which outside air is introduced as a cooling gas into the exterior housing, and a discharge port via which the cooling gas is discharged, a first cooling target disposed at the inner surface of the first wall, a cooling fan including an intake portion that sucks the cooling gas and a sending portion that sends the sucked cooling gas, a first flow path that cause the cooling gas to flow between the introduction port and the intake portion, and a second flow path that cause the cooling gas to flow between the sending portion and the discharge port. The first flow path is formed by a first surface of the first cooling target, and the second flow path is formed by a second surface different from the first surface in the first cooling target.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Toshio MATSUMIYA, Keita TSUKIOKA, Yosuke NAKATA, Nobuyuki OTSUKI
  • Patent number: 12009332
    Abstract: A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). An intermediate plate (6) is provided in the first solder (2) between the electrode substrate (1) and the semiconductor chip (3). A yield strength of the intermediate plate (6) is higher than yield strengths of the electrode substrate (1) and the first solder (2) within the whole operating temperature range of the semiconductor device.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 11, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Taishi Sasaki
  • Publication number: 20240079384
    Abstract: An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surface of the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 7, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke NAKATA, Jun FUJITA
  • Patent number: 11901341
    Abstract: An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 13, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Jun Fujita
  • Publication number: 20240047318
    Abstract: An object is to provide a technique capable of reducing stress in the entire semiconductor device. The semiconductor device includes a plurality of sub-modules including a first sealing member, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductive plates of the plurality of sub-modules, connection members electrically connected to at least one of the conductive pieces of the plurality of sub-modules, and a second sealing member having lower hardness than the first sealing member, which seals the plurality of sub-modules, the insulating substrate, and the connection members.
    Type: Application
    Filed: May 11, 2023
    Publication date: February 8, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke NAKATA, Yuji SATO, Taketoshi SHIKANO
  • Publication number: 20240047430
    Abstract: An object is to provide a technique capable of easily taking out a submodule from a semiconductor device to reuse the submodule. The semiconductor device includes: a submodule in which a conductive plate and a semiconductor element mounted to an upper surface of the conductive plate via a first bonding material are sealed with a first sealing material; an insulating substrate bonded to a lower surface of the submodule via a second bonding material; a case surrounding a periphery of the insulating substrate and the submodule; and a second sealing material sealing a region surrounded by the case so that at least an upper surface of the submodule is exposed.
    Type: Application
    Filed: April 25, 2023
    Publication date: February 8, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke NAKATA, Norikazu SAKAI, Yuji SATO, Yoshinori YOKOYAMA
  • Patent number: 11887933
    Abstract: A semiconductor chip including a main electrode and a control electrode is bonded to a substrate. A wiring chip including a first electrode, a second electrode and a wiring is bonded to the substrate. A main electrode member is bonded to the main electrode. A control electrode member is bonded to the second electrode. The control electrode is bonded to the first electrode with a connection member. The semiconductor chip, the substrate, the wiring chip, the main electrode member, the control electrode member and the connection member are putted into a mold and are sealed with sealing material by injecting the sealing material into the mold in a state that distal end surfaces of the main electrode member and the control electrode member are pressed against a buffer material provided between the main electrode member/the control electrode member and the mold. The sealing material is not ground.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: January 30, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Yuji Sato
  • Patent number: 11848298
    Abstract: A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other,
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: December 19, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Yuji Sato, Yoshinori Yokoyama
  • Patent number: 11777419
    Abstract: A semiconductor device includes: a semiconductor substrate in which a cell region, an isolation region being a region which is located outward of the cell region, and a termination region including a guard ring region being located outward of the isolation region and an excess region being a region which is located outward of the guard ring region are defined; an insulating layer covering a top surface of the semiconductor substrate in the isolation region and the termination region; a surface electrode located on a portion of the top surface of the semiconductor substrate and a portion of a top surface of the insulating layer in the cell region and the isolation region; and a waterproof layer covering a portion of the insulating layer exposed from the surface electrode. The waterproof layer is spaced apart from the surface electrode.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: October 3, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Publication number: 20230238295
    Abstract: An object is to provide a technique which suppresses peeling between a sealing resin and a semiconductor element while suppressing a decrease in productivity and an increase in manufacturing cost in a semiconductor device. A semiconductor device includes a semiconductor element, and a sealing resin sealing the semiconductor element. The semiconductor element includes a cell region through which a main current flows, a terminal region provided on an outer peripheral side of the cell region, and a protective film covering an upper surface of an outer peripheral portion of the terminal region. The protective film includes spread portions spreading to outermost ends at four corners of the semiconductor element. The spread portions have a cut section continuous with a cut section of the terminal region, and do not spread to the outermost ends in four sides excluding the four corners of the semiconductor element.
    Type: Application
    Filed: November 17, 2022
    Publication date: July 27, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yosuke NAKATA
  • Publication number: 20230065822
    Abstract: A semiconductor device includes: a semiconductor substrate in which a cell region, an isolation region being a region which is located outward of the cell region, and a termination region including a guard ring region being located outward of the isolation region and an excess region being a region which is located outward of the guard ring region are defined; an insulating layer covering a top surface of the semiconductor substrate in the isolation region and the termination region; a surface electrode located on a portion of the top surface of the semiconductor substrate and a portion of a top surface of the insulating layer in the cell region and the isolation region; and a waterproof layer covering a portion of the insulating layer exposed from the surface electrode. The waterproof layer is spaced apart from the surface electrode.
    Type: Application
    Filed: June 8, 2022
    Publication date: March 2, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yosuke NAKATA
  • Patent number: 11508698
    Abstract: Each of a plurality of semiconductor elements included in a semiconductor package includes a front-surface electrode being provided on a semiconductor substrate on a side opposite to a conductor substrate, a back-surface electrode being joined to the conductor substrate, a control pad configured to control current flowing between the front-surface electrode and the back-surface electrode, a frame being electrically connected to the front-surface electrode, a portion of the frame being exposed from a surface of a sealing material from which a lower surface of the conductor substrate is exposed, and a plurality of terminal blocks being electrically connected to a plurality of first pads, a portion of the plurality of terminal blocks being exposed from a surface of the sealing material, the surface being provided on a side opposite to the surface of the sealing material from which the lower surface of the conductor substrate is exposed.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: November 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 11462516
    Abstract: An object of the present disclosure is to provide a method of manufacturing a semiconductor device capable of suppressing an electrostatic breakdown in a configuration including a semiconductor element with a sense cell part. A method of manufacturing a semiconductor device according to the present disclosure includes: bonding each of semiconductor elements 1 and a relay substrate on a conductor plate; connecting each of signal pads of each of the semiconductor elements and each of control pads of the relay substrate by a wire; bonding a first electrode material on each of the semiconductor elements; bonding a second electrode material on the relay substrate; sealing the conductor plate, each of the semiconductor elements, the relay substrate, the first electrode material, and the second electrode material by a sealing resin; and grinding the sealing resin and removing the shorting part to expose part of the second electrode material.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: October 4, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Publication number: 20220302036
    Abstract: A semiconductor chip including a main electrode and a control electrode is bonded to a substrate. A wiring chip including a first electrode, a second electrode and a wiring is bonded to the substrate. A main electrode member is bonded to the main electrode. A control electrode member is bonded to the second electrode. The control electrode is bonded to the first electrode with a connection member. The semiconductor chip, the substrate, the wiring chip, the main electrode member, the control electrode member and the connection member are putted into a mold and are sealed with sealing material by injecting the sealing material into the mold in a state that distal end surfaces of the main electrode member and the control electrode member are pressed against a buffer material provided between the main electrode member/the control electrode member and the mold. The sealing material is not ground.
    Type: Application
    Filed: October 14, 2021
    Publication date: September 22, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke NAKATA, Yuji SATO
  • Patent number: 11450592
    Abstract: A semiconductor device according to the disclosure includes a first semiconductor chip, a second semiconductor chip, a first metal plate provided on an upper surface of the first semiconductor chip, a second metal plate provided on an upper surface of the second semiconductor chip and a sealing resin covering the first semiconductor chip, the second semiconductor chip, the first metal plate and the second metal plate, wherein a groove is formed in the sealing resin, the groove extending downwards from an upper surface of the sealing resin, the first metal plate includes, at an end facing the second metal plate, a first exposed portion exposed from a side face of the sealing resin forming the groove, and the second metal plate includes, at an end facing the first metal plate, a second exposed portion exposed from a side face of the sealing resin forming the groove.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 20, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroya Sannai, Kei Hayashi, Yosuke Nakata, Tatsuya Kawase, Yuji Imoto
  • Patent number: 11430726
    Abstract: A semiconductor device (4a-4d) and a wiring device (5) are provided on a main surface of a base plate (1). A first wire (11a-11e) connects an external electrode (7a-7e) and a first relay pad (8a-8e) of the wiring device (5). A second wire (12a-12e) connects a pad (13a-13e) of the semiconductor device (4a-4d) and the second relay pad (9a-9e) of the wiring device (5). Resin (15) seals the semiconductor device (4a-4d), the wiring device (5) and the first and second wires (11a-11e,12a-12e). The second wire (12a-12e) is thinner than the first wire (11a-11e). The pad (13a-13e) is smaller than the first relay pad (8a-8e).
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 30, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Publication number: 20220238476
    Abstract: A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other,
    Type: Application
    Filed: August 13, 2021
    Publication date: July 28, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Yuji Sato, Yoshinori Yokoyama
  • Patent number: 11387158
    Abstract: The semiconductor device includes a substrate, a semiconductor element bonded to the substrate, and a sealing resin sealing at least a part of the substrate and the semiconductor element, in which the semiconductor element includes an active region through which a main current flows in an ON state of the semiconductor element, a terminal region surrounding the active region, an anchor film provided on an insulating film of the terminal region, and a protective film covering at least the terminal region including the anchor film, and the anchor film consists of a material different from the insulating film and has a plurality of openings provided discretely.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 11302538
    Abstract: A semiconductor device manufacturing method includes processes of: applying a protective film precursor solution over an end of each of a plurality of semiconductor element structures and a side surface and a bottom surface of a groove; roughly drying a solvent in the protective film precursor solution to form a protective film; and performing full-curing to evaporate a solvent in the protective film after a process of cutting between the plurality of semiconductor element structures or a process of peeling a plurality of semiconductor elements from a dicing tape.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata