Abstract: According to one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first end, a second end, and a first body. The second transistor includes a third end coupled to the second end, a fourth end, and a second body. The semiconductor device includes a first resistor coupled to the first end, a second resistor coupled between the first resistor and the second end, a third resistor coupled to the third end, a fourth resistor coupled between the third resistor and the fourth end, a first diode coupled between the first body and a node coupling the third resistor and the fourth resistor, and a second diode coupled between the second body and a node coupling the first resistor and the second resistor.

Abstract: In general, according to one embodiment, a semiconductor device includes an input terminal, an output terminal, and a plurality of transistors. The transistors are coupled through serial coupling. The transistors include a first transistor and a second transistor. The first transistor has a first end and a second end. The second transistor has a third end, a fourth end, a first gate, and a first body. The third end is coupled to the second end. The semiconductor device further includes a third transistor and a first diode. The third transistor and the first diode are serially coupled between the first body and the first end. The third transistor includes a second gate coupled to the first gate.

Abstract: According to one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first end, a second end, and a first body. The second transistor includes a third end coupled to the second end, a fourth end, and a second body. The semiconductor device includes a first resistor coupled to the first end, a second resistor coupled between the first resistor and the second end, a third resistor coupled to the third end, a fourth resistor coupled between the third resistor and the fourth end, a first diode coupled between the first body and a node coupling the third resistor and the fourth resistor, and a second diode coupled between the second body and a node coupling the first resistor and the second resistor.

Abstract: A distance measuring device according to an embodiment includes a filter, a first switching circuit, an impedance adjustable circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit. The filter restricts a signal for distance measurement transmitted from the transmission circuit and a signal for distance measurement received by an antenna within a desired frequency band. The impedance adjustable circuit is adjusted to have a higher impedance than an impedance of the antenna. The second switching circuit switches conduction and non-conduction between the impedance adjustable circuit and the transmission circuit. The third switching circuit switches conduction and non-conduction between the impedance adjustable circuit and the reception circuit. The fourth switching circuit switches conduction and non-conduction between the impedance adjustable circuit and the second switching circuit and between the impedance adjustable circuit and the third switching circuit.

Abstract: A distance measuring device according to an embodiment includes a filter, a first switching circuit, an impedance adjustable circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit. The filter restricts a signal for distance measurement transmitted from the transmission circuit and a signal for distance measurement received by an antenna within a desired frequency band. The impedance adjustable circuit is adjusted to have a higher impedance than an impedance of the antenna. The second switching circuit switches conduction and non-conduction between the impedance adjustable circuit and the transmission circuit. The third switching circuit switches conduction and non-conduction between the impedance adjustable circuit and the reception circuit. The fourth switching circuit switches conduction and non-conduction between the impedance adjustable circuit and the second switching circuit and between the impedance adjustable circuit and the third switching circuit.

Abstract: A clock generation circuit includes a random number generator configured to generate random numbers according to a first probability distribution, a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto, and a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution. Probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.

Abstract: A clock circuit includes a selector circuit connected to an output terminal, first, second, and third paths connected in parallel between an input terminal for receiving an input clock signal and the selector circuit, a first clock signal output from the first path being delayed with respect to a second clock signal output from the second path by a predetermined length of time, and the second clock signal being delayed with respect to a third clock signal output from the third path by the predetermined length of time, and a control circuit configured to control the selector circuit to switch among at least two of the first, second, and third clock signals.

Abstract: A clock circuit includes a selector circuit connected to an output terminal, first, second, and third paths connected in parallel between an input terminal for receiving an input clock signal and the selector circuit, a first clock signal output from the first path being delayed with respect to a second clock signal output from the second path by a predetermined length of time, and the second clock signal being delayed with respect to a third clock signal output from the third path by the predetermined length of time, and a control circuit configured to control the selector circuit to switch among at least two of the first, second, and third clock signals.

Abstract: A clock generation circuit includes a random number generator configured to generate random numbers according to a first probability distribution, a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto, and a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution. Probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: According to one embodiment, a complex band pass filter comprises a first active filter circuit 10 to receive a first input signal on its input end and a second active filter circuit 20 to receive a second input signal on its input end, the second input signal having a 90-degree phase difference from the first input signal. A predetermined offset is imparted to the first input signal and the second input signal through the first and second signal level adjusting units (30, 40). A differential signal between the output signals of the first and second active filter circuits (10, 20) is outputted.

Abstract: According to one embodiment, a complex band pass filter comprises a first active filter circuit 10 to receive a first input signal on its input end and a second active filter circuit 20 to receive a second input signal on its input end, the second input signal having a 90-degree phase difference from the first input signal. A predetermined offset is imparted to the first input signal and the second input signal through the first and second signal level adjusting units (30, 40). A differential signal between the output signals of the first and second active filter circuits (10, 20) is outputted.

Abstract: According to one embodiment, an analog unit performs frequency conversion of a reception signal. A digital unit performs demodulation processing of the reception signal subjected to the frequency conversion by the analog unit. A PLL circuit generates a clock of the digital unit. A PLL-setting changing unit performs, based on the reception signal, a setting change of parameters of the PLL circuit to thereby control the jitter of the clock.

Abstract: According to one embodiment, there is provided a semiconductor device including a first amplifier and a second amplifier. The first amplifier has an input terminal to receive a first signal and an output terminal to output a second signal. The second amplifier is configured to receive the first signal and a correction data, to generate a correction signal according to the first signal and the correction data, and to output the generated correction signal to the output terminal of the first amplifier so as to add the first signal and the generated correction signal.

Abstract: A differential amplifier circuit includes a source follower circuit to which is input one of the differential signals and a common source circuit that is connected in series with the source follower circuit and to which is input the other of the differential signals.

Abstract: According to one embodiment, there is provided a semiconductor device including a first amplifier and a second amplifier. The first amplifier has an input terminal to receive a first signal and an output terminal to output a second signal. The second amplifier is configured to receive the first signal and a correction data, to generate a correction signal according to the first signal and the correction data, and to output the generated correction signal to the output terminal of the first amplifier so as to add the first signal and the generated correction signal.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

Abstract: According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.