Patents by Inventor You-Cheng Xiao
You-Cheng Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230289508Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.Type: ApplicationFiled: June 29, 2022Publication date: September 14, 2023Inventors: Chi-Yeh Yu, Wei-Yi Hu, Shih-Hsuan Chien, You-Cheng Xiao, Ya-Chi Chou
-
Publication number: 20230124337Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
-
Publication number: 20230111939Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
-
Publication number: 20230042514Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.Type: ApplicationFiled: January 21, 2022Publication date: February 9, 2023Inventors: Ru-Yu WANG, You-Cheng XIAO, Kao-Cheng LIN, Pin-Dai SUE, Ting-Wei CHIANG
-
Patent number: 11552085Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.Type: GrantFiled: September 28, 2020Date of Patent: January 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng Xiao, Jhih-Siang Hu, Ru-Yu Wang, Jung-Hsuan Chen, Ting-Wei Chiang
-
Publication number: 20220302136Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.Type: ApplicationFiled: August 17, 2021Publication date: September 22, 2022Inventors: Po-Sheng WANG, Ru-Yu WANG, Yangsyu LIN, You-Cheng XIAO
-
Publication number: 20220102363Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.Type: ApplicationFiled: September 28, 2020Publication date: March 31, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
-
Patent number: 9530727Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.Type: GrantFiled: May 11, 2015Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Cheng Xiao, Wei Min Chan, Ken-Hsien Hsieh
-
Patent number: 9425095Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: GrantFiled: May 24, 2015Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
-
Publication number: 20150255338Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: ApplicationFiled: May 24, 2015Publication date: September 10, 2015Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
-
Publication number: 20150243600Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.Type: ApplicationFiled: May 11, 2015Publication date: August 27, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Wei Min CHAN, Ken-Hsien HSIEH
-
Patent number: 9041069Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: GrantFiled: January 14, 2011Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
-
Patent number: 9029230Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.Type: GrantFiled: January 31, 2013Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Cheng Xiao, Wei Min Chan, Ken-Hsien Hsieh
-
Patent number: 8837250Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.Type: GrantFiled: July 20, 2010Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: You-Cheng Xiao, Hong-Chen Cheng, Chung-Ji Lu, Cheng Hung Lee, Jung-Hsuan Chen, Li-Chun Tien
-
Publication number: 20140210100Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: You-Cheng XIAO, Wei Min CHAN, Ken-Hsien HSIEH
-
Patent number: 8692333Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.Type: GrantFiled: August 12, 2010Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Huei Chen, You-Cheng Xiao, Jung-Hsuan Chen, Shao-Yu Chou
-
Publication number: 20120181707Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
-
Publication number: 20120037997Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.Type: ApplicationFiled: August 12, 2010Publication date: February 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Huei CHEN, You-Cheng XIAO, Jung-Hsuan CHEN, Shao-Yu CHOU
-
Publication number: 20120020179Abstract: A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.Type: ApplicationFiled: July 20, 2010Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACURING CO., LTD.Inventors: You-Cheng XIAO, Hong-Chen CHENG, Chung-Ji LU, Cheng Hung LEE, Jung-Hsuan CHEN, Li-Chun TIEN
-
Patent number: 8013770Abstract: A digital-to-analog converter (DAC) for converting a digital signal to an analog signal includes a first thermometer decoder and a second thermometer decoder. The first thermometer decoder is configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code. The second thermometer decoder is configured to decode middle bits of the digital signal to generate a second thermometer code. The DAC further includes a plurality of macro cells with each controlled by one bit of the first thermometer code. The plurality of macro cells is configured to provide a first analog signal according to the first thermometer code. The DAC further includes a macro cell configured to provide a second analog signal according to the second thermometer code. The macro cell is further configured to provide a third analog signal according to least-significant bits (LSBs) of the digital signal.Type: GrantFiled: December 9, 2008Date of Patent: September 6, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Robit Yang, Ying-Chi Hsu, You-Cheng Xiao, Wen-Shen Chou