Patents by Inventor You-Cheol Shin
You-Cheol Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7144790Abstract: A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 ? or more, and is preferably made at a middle area. Conventionally, a gate insulating layer includes a thin area of about 100 ? or less and a thick area of about 200 ? or more. On the basis of a bottom of a trench peripheral region, a middle part of the flexure may be concave or convex. Particularly, the foregoing device can effectively be applied to a self-aligned flash memory in which a width of a trench between one active region and another is about 3 micrometers or less.Type: GrantFiled: April 4, 2003Date of Patent: December 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: You-Cheol Shin
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Patent number: 6960500Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.Type: GrantFiled: February 11, 2004Date of Patent: November 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Kyu-Charn Park, Won-Hong Lee, Jung-Dal Choi
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Patent number: 6784055Abstract: A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.Type: GrantFiled: April 18, 2003Date of Patent: August 31, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Jong-Woo Park, Jung-Dal Choi
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Patent number: 6784481Abstract: A flash memory having a charge-storage dielectric layer. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.Type: GrantFiled: March 15, 2002Date of Patent: August 31, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Jong-Woo Park, Jung-Dal Choi
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Publication number: 20040161881Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.Type: ApplicationFiled: February 11, 2004Publication date: August 19, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Kyu-Charn Park, Won-Hong Lee, Jung-Dal Choi
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Patent number: 6750525Abstract: A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure is provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can also be thinner than the equivalent thickness of the cell gate insulation layer.Type: GrantFiled: March 15, 2002Date of Patent: June 15, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Patent number: 6734065Abstract: Embodiments of the invention provide a method that includes forming a selection transistor and a cell transistor that includes a cell gate insulation layer in a cell array area. The method also includes forming a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer in a peripheral circuit area. The low-voltage gate insulation layer is formed thinner than the high-voltage gate insulation layer. The low voltage gate insulation layer may also be formed thinner than the equivalent thickness of the cell gate insulation layer.Type: GrantFiled: April 18, 2003Date of Patent: May 11, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Patent number: 6720579Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.Type: GrantFiled: January 7, 2002Date of Patent: April 13, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Kyu-Charn Park, Won-Hong Lee, Jung-Dal Choi
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Publication number: 20030205727Abstract: A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.Type: ApplicationFiled: April 18, 2003Publication date: November 6, 2003Applicant: Samsung Electronics Co., LtdInventors: You-Cheol Shin, Jong-Woo Park, Jung-Dal Choi
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Publication number: 20030205728Abstract: A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure and a fabrication method thereof are provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can be also thinner than the equivalent thickness of the cell gate insulation layer.Type: ApplicationFiled: April 18, 2003Publication date: November 6, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Publication number: 20030201511Abstract: A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 Å or more, and is preferably made at a middle area. Conventionally, a gate insulating layer includes a thin area of about 100 Å or less and a thick area of about 200 Å or more. On the basis of a bottom of a trench peripheral region, a middle part of the flexure may be concave or convex. Particularly, the foregoing device can effectively be applied to a self-aligned flash memory in which a width of a trench between one active region and another is about 3 micrometers or less.Type: ApplicationFiled: April 4, 2003Publication date: October 30, 2003Applicant: Samsung Electronics Co., Ltd.Inventor: You-Cheol Shin
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Publication number: 20020130350Abstract: A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.Type: ApplicationFiled: March 15, 2002Publication date: September 19, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Jong-Woo Park, Jung-Dal Choi
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Publication number: 20020130314Abstract: A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure and a fabrication method thereof are provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can be also thinner than the equivalent thickness of the cell gate insulation layer.Type: ApplicationFiled: March 15, 2002Publication date: September 19, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Sik Yim, Jung-Dal Choi, Hong-Suk Kwack, You-Cheol Shin
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Publication number: 20020088976Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.Type: ApplicationFiled: January 7, 2002Publication date: July 11, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: You-Cheol Shin, Kyu-Charn Park, Won-Hong Lee, Jung-Dal Choi
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Publication number: 20020024111Abstract: A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 Å or more, and is preferably made at a middle area. Conventionally, a gate insulating layer includes a thin area of about 100 Å or less and a thick area of about 200 Å or more. On the basis of a bottom of a trench peripheral region, a middle part of the flexure may be concave or convex. Particularly, the foregoing device can effectively be applied to a self-aligned flash memory in which a width of a trench between one active region and another is about 3 micrometers or less.Type: ApplicationFiled: March 28, 2001Publication date: February 28, 2002Applicant: Samsung Electronics Co., Ltd.Inventor: You-Cheol Shin