Abstract: Disclosed is a QFN packaged semiconductor device, having a first major surface, an opposing second major surface and sidewalls therebetween, and comprising: a lead-frame, having a lead-frame lower surface and comprising a central die-pad region and a plurality of peripheral landing regions; a semiconductor die, attached to the die-pad on a top surface thereof; a plurality of bond-wires providing electrical connection between the semiconductor die and the plurality of peripheral landing regions; and encapsulant material, encapsulating the semiconductor die and bond-wires; wherein the encapsulant material forms a frame extending below the lead-frame lower surface, and defining the second major surface, the frame having an opening therein in a central region thereof under the semiconductor die, and wherein the sidewalls are spaced apart from the frame thereby exposing the lead-frame lower surface at the plurality of peripheral landing regions.

Abstract: A packaged semiconductor device is disclosure having a first major package surface and a second major package surface and comprising: an encapsulated die having a plurality of die contact pads on a first major die surface thereof; a molding compound; and a plurality of exposed solder pads each comprising a flattened lower surface of wedge-bond wire; wherein the plurality of exposed solder pads are around a peripheral region of the second major package surface and spaced apart by the molding compound; and wherein the plurality of solder pads are electrically connected to the contact pads by at least one set of bond wires. Corresponding methods are also disclosed.

Abstract: A packaged semiconductor device has a top surface and a bottom surface opposite the top surface. The packaged semiconductor device includes a device die, a plurality of perimeter landings, connection lines, and molding compound. The device die has a first surface and a second surface opposite the first surface. The device die is arranged in a central region of the packaged semiconductor device. The first surface of the device die is arranged towards the bottom surface of the packaged semiconductor device, and the second surface of the device die is arranged towards the top surface of the packaged semiconductor device. The plurality of perimeter landings are exposed on the bottom surface of the packaged semiconductor device and are arranged at perimeter regions of the bottom surface surrounding the device die. The connection lines are connected to the second surface of the device die.

Abstract: According to a first aspect of the present invention there is provided a QFN packaged semiconductor device having a QFN bottom surface, the QFN packaged semiconductor device comprising: a die pad on the QFN bottom surface; a die on the die pad; a plurality of leads spaced apart from the die pad and around a periphery of the QFN bottom surface; a plurality of bond wires connecting the die and the leads; a molding compound covering the die and the bond wires, which having an central region and a peripheral region, each central region having a first top surface and first side faces, each peripheral region having a second top surface and second side faces, wherein the height of the peripheral region is lower than that of the central region.

Abstract: A packaged semiconductor device has a first surface, a second surface opposite the first surface, and sidewalls therebetween. The semiconductor device includes: a device die arranged in a central region surrounded by the sidewalls; a plurality of electrically conductive contacts around a peripheral region of the second surface; and molding compound between electrically conductive contacts, and between the device die and the electrically conductive contacts. The electrically conductive contacts each have an end side surface forming a part of the sidewall, and remainder of the sidewall comprises surfaces of the molding compound. The packaged semiconductor device has recesses between the electrically conductive contacts, each recess has a first distance along the sidewall from the second surface towards the first surface, and a second distance from the sidewall towards the central region.

Abstract: Disclosed is a packaged semiconductor device having first and second major surfaces and comprising, a semiconductor die; conductive epoxy in contact with a surface of the semiconductor die, and exposed in a central region of the first major surface; a plurality of studs around a peripheral region of the first major surface; wire bonds between the semiconductor die and a surface of the studs which is remote from the first major surface, the wire bonds providing electrical connections between the semiconductor die and the plurality of studs; and encapsulant defining the second major surface and sidewalls of the packaged semiconductor device, wherein the first major surface is defined by the conductive epoxy, the encapsulant, and the studs.

Abstract: A Quad Flat No-Lead (QFN) package comprises a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat.

Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Abstract: A method of packaging a semiconductor device includes: bonding a ball at an end of a bond wire to a bond pad of a semiconductor device die in an aperture of a shielding layer of the semiconductor device; and sealing the part of the bond pad exposed by the aperture of the shielding layer by deforming the ball of the bond wire to fill the aperture of the shielding layer. The aperture of the shielding layer includes an edge wall, and exposes a part of the bond pad. The shielding layer covers a remaining part of the bond pad. The aperture of the shielding layer is completely filled with the ball of the bond wire, thereby deforming the edge wall of the shielding layer.

Abstract: According to a first aspect of the present invention there is provided a quad-flat-no-leads (QFN) packaged semiconductor device having a QFN bottom surface and QFN side faces, wherein the QFN side faces each comprise an upper portion and a recessed lower portion, the QFN packaged semiconductor device comprising: a die pad within or on the QFN bottom surface; a plurality of I/O terminals spaced apart from the die pad and around a periphery of the bottom surface, each having a bottom face extending from an inner end to a peripheral end, an exposed side face on a QFN side face and extending above the recessed lower portion of the QFN side face; wherein the QFN bottom surface includes at least one trench therein, parallel to a one of the QFN side faces and exposing at least a part of a side face of the inner end of the I/O terminals. The trench may provide for additional surface area, and provide a stronger solder joint when the QFN packaged semiconductor device is soldered to a substrate or circuit board.

Abstract: According to a first aspect of the present invention there is provided a semiconductor device comprising: a die having a central active region, a top surface, a bottom surface, and sidewalls having a plurality of perforations therein, each perforation extending from a top end at the top surface to a bottom end at the bottom surface; a plurality of die pads on the top surface and extending from the central active region to respective top ends; a patterned back-side-metallization layer on the bottom surface, comprising a plurality of electrically isolated regions extending to respective bottom ends; metal coating partially filling the perforations and providing electrical connection between respective ones of the plurality of die pads and respective ones of the plurality of electrically isolated regions; and a passivation layer covering the top surface and the die pads.

Abstract: There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.

Abstract: A power die package includes a lead frame having a flag with power leads on one lateral side and signal leads on one or more other lateral sides. A power die is attached to a bottom surface of the flag and electrically connected to the power leads with a conductive epoxy. A control die is attached to a top surface of the flag and electrically connected to the signal leads with bond wires. A mold compound is provided that encapsulates the dies, the bond wires, and proximal parts of the leads, while distal ends of the leads are exposed, forming a PQFN package.

Abstract: Disclosed are a base station and a cleaning system. The base station is configured for pumping dirt from a cleaning robot and injecting water to the cleaning robot, and the cleaning robot is defined with a host dirt collecting chamber and a host clean water chamber. The base station includes a base station body, a dirt pumping assembly and a water injection assembly. The dirt pumping assembly is arranged in the base station body, and can move relative to the base station body and communicate with the host dirt collecting chamber; The water injection assembly is arranged in the base station body, and can move relative to the base station body and communicate with the host clean water chamber. The technical solution of the present application can make the use function of the base station more diversified, and improve the practicability of the base station.

Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.

Abstract: A Quad Flat No-Lead (QFN) package comprises a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat.

Abstract: A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.

Abstract: A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.

Abstract: A power die package includes a lead frame having a flag with power leads on one lateral side and signal leads on one or more other lateral sides. A power die is attached to a bottom surface of the flag and electrically connected to the power leads with a conductive epoxy. A control die is attached to a top surface of the flag and electrically connected to the signal leads with bond wires. A mold compound is provided that encapsulates the dies, the bond wires, and proximal parts of the leads, while distal ends of the leads are exposed, forming a PQFN package.