Patents by Inventor You Ge
You Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230124619Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.Type: ApplicationFiled: November 2, 2021Publication date: April 20, 2023Inventors: You Ge, Zhijie Wang, Yit Meng Lee, Mariano Layson Ching, JR.
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Publication number: 20230110402Abstract: A method of packaging a semiconductor device includes: bonding a ball at an end of a bond wire to a bond pad of a semiconductor device die in an aperture of a shielding layer of the semiconductor device; and sealing the part of the bond pad exposed by the aperture of the shielding layer by deforming the ball of the bond wire to fill the aperture of the shielding layer. The aperture of the shielding layer includes an edge wall, and exposes a part of the bond pad. The shielding layer covers a remaining part of the bond pad. The aperture of the shielding layer is completely filled with the ball of the bond wire, thereby deforming the edge wall of the shielding layer.Type: ApplicationFiled: October 6, 2022Publication date: April 13, 2023Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Publication number: 20230115182Abstract: According to a first aspect of the present invention there is provided a quad-flat-no-leads (QFN) packaged semiconductor device having a QFN bottom surface and QFN side faces, wherein the QFN side faces each comprise an upper portion and a recessed lower portion, the QFN packaged semiconductor device comprising: a die pad within or on the QFN bottom surface; a plurality of I/O terminals spaced apart from the die pad and around a periphery of the bottom surface, each having a bottom face extending from an inner end to a peripheral end, an exposed side face on a QFN side face and extending above the recessed lower portion of the QFN side face; wherein the QFN bottom surface includes at least one trench therein, parallel to a one of the QFN side faces and exposing at least a part of a side face of the inner end of the I/O terminals. The trench may provide for additional surface area, and provide a stronger solder joint when the QFN packaged semiconductor device is soldered to a substrate or circuit board.Type: ApplicationFiled: September 15, 2022Publication date: April 13, 2023Inventors: Meng Kong Lye, Zhijie Wang, You Ge, Zhiming Li
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Publication number: 20230097173Abstract: According to a first aspect of the present invention there is provided a semiconductor device comprising: a die having a central active region, a top surface, a bottom surface, and sidewalls having a plurality of perforations therein, each perforation extending from a top end at the top surface to a bottom end at the bottom surface; a plurality of die pads on the top surface and extending from the central active region to respective top ends; a patterned back-side-metallization layer on the bottom surface, comprising a plurality of electrically isolated regions extending to respective bottom ends; metal coating partially filling the perforations and providing electrical connection between respective ones of the plurality of die pads and respective ones of the plurality of electrically isolated regions; and a passivation layer covering the top surface and the die pads.Type: ApplicationFiled: September 14, 2022Publication date: March 30, 2023Inventors: You Ge, Zhijie Wang, Yit Meng Lee
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Publication number: 20230068886Abstract: There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.Type: ApplicationFiled: August 10, 2022Publication date: March 2, 2023Inventors: You Ge, Zhijie Wang, Yit Meng Lee, Yanbo Xu
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Patent number: 11515238Abstract: A power die package includes a lead frame having a flag with power leads on one lateral side and signal leads on one or more other lateral sides. A power die is attached to a bottom surface of the flag and electrically connected to the power leads with a conductive epoxy. A control die is attached to a top surface of the flag and electrically connected to the signal leads with bond wires. A mold compound is provided that encapsulates the dies, the bond wires, and proximal parts of the leads, while distal ends of the leads are exposed, forming a PQFN package.Type: GrantFiled: June 17, 2020Date of Patent: November 29, 2022Assignee: NXP USA, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang, Kabir Mirpuri
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Publication number: 20220338702Abstract: Disclosed are a base station and a cleaning system. The base station is configured for pumping dirt from a cleaning robot and injecting water to the cleaning robot, and the cleaning robot is defined with a host dirt collecting chamber and a host clean water chamber. The base station includes a base station body, a dirt pumping assembly and a water injection assembly. The dirt pumping assembly is arranged in the base station body, and can move relative to the base station body and communicate with the host dirt collecting chamber; The water injection assembly is arranged in the base station body, and can move relative to the base station body and communicate with the host clean water chamber. The technical solution of the present application can make the use function of the base station more diversified, and improve the practicability of the base station.Type: ApplicationFiled: December 3, 2021Publication date: October 27, 2022Applicant: SUZHOU 360 ROBOTIC TECHNOLOGY CO.,LTDInventors: Jixin WANG, Lianbin XU, Yongbin YANG, Suijun WEI, You GE
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Patent number: 11456188Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.Type: GrantFiled: May 14, 2020Date of Patent: September 27, 2022Assignee: NXP USA, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Publication number: 20220077052Abstract: A Quad Flat No-Lead (QFN) package comprises a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat.Type: ApplicationFiled: July 28, 2021Publication date: March 10, 2022Inventors: You Ge, Zhijie Wang, Meng Kong Lye
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Patent number: 11171077Abstract: A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.Type: GrantFiled: June 22, 2020Date of Patent: November 9, 2021Assignee: NXP USA, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Publication number: 20210013137Abstract: A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.Type: ApplicationFiled: June 22, 2020Publication date: January 14, 2021Inventors: You GE, Meng Kong LYE, Zhijie WANG
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Publication number: 20200411423Abstract: A power die package includes a lead frame having a flag with power leads on one lateral side and signal leads on one or more other lateral sides. A power die is attached to a bottom surface of the flag and electrically connected to the power leads with a conductive epoxy. A control die is attached to a top surface of the flag and electrically connected to the signal leads with bond wires. A mold compound is provided that encapsulates the dies, the bond wires, and proximal parts of the leads, while distal ends of the leads are exposed, forming a PQFN package.Type: ApplicationFiled: June 17, 2020Publication date: December 31, 2020Inventors: You Ge, Meng Kong Lye, Zhijie Wang, Kabir Mirpuri
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Publication number: 20200312751Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.Type: ApplicationFiled: May 14, 2020Publication date: October 1, 2020Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Patent number: 10692802Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.Type: GrantFiled: November 30, 2016Date of Patent: June 23, 2020Assignee: NXP USA, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Patent number: 10217697Abstract: A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second direction. Each lead includes a bond pad portion and a solder pad portion down-set from the bond pad portion. The solder pad portion horizontally extends from the bond pad portion in the first direction. A semiconductor die is mounted on a set of the plurality of leads and electrically connected to the bond pad portion of at least one of the plurality of leads. The semiconductor die, and the plurality of leads are encapsulated by a molding material, wherein the molding material defines a package body, and the solder pad portion of each lead is exposed at a back side of the package body.Type: GrantFiled: December 15, 2016Date of Patent: February 26, 2019Assignee: NXP B.V.Inventors: Zhijie Wang, Zhigang Bai, You Ge, Meng Kong Lye
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Patent number: 10041195Abstract: A woven signal-routing substrate for a wearable electronic device has conductive warps and wefts that are woven with each other and with insulative warps and wefts. Woven electrical cross-connections are formed at some of the intersections of the conductive warps and wefts, while no electrical cross-connections are formed at other intersections, to provide a signal-routing architecture for the substrate that can be used to route signals between electronic components of the wearable device. Non-connecting intersections are formed using insulative warps that are sufficiently thicker than the relatively thin conductive warps to enable a conductive weft to cross a conductive warp without making physical contact at intersection locations where an electrical cross-connection is not desired. The woven electrical cross-connections may be formed at other intersection locations using weaving topologies that ensure that the corresponding mutually orthogonal warps and wefts do contact one another.Type: GrantFiled: January 6, 2016Date of Patent: August 7, 2018Assignee: NXP USA, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Publication number: 20180102305Abstract: A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second direction. Each lead includes a bond pad portion and a solder pad portion down-set from the bond pad portion. The solder pad portion horizontally extends from the bond pad portion in the first direction. A semiconductor die is mounted on a set of the plurality of leads and electrically connected to the bond pad portion of at least one of the plurality of leads. The semiconductor die, and the plurality of leads are encapsulated by a molding material, wherein the molding material defines a package body, and the solder pad portion of each lead is exposed at a back side of the package body.Type: ApplicationFiled: December 15, 2016Publication date: April 12, 2018Inventors: ZHIJIE WANG, ZHIGANG BAI, YOU GE, MENG KONG LYE
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Publication number: 20170358525Abstract: A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached to the first tape and electrically connected to the bond pads by way of electrical contacts. A second tape is attached to a top surface of the semiconductor die. The first and second tapes encapsulate the semiconductor die, the electrical contacts, and at least a part of the conductive traces.Type: ApplicationFiled: November 30, 2016Publication date: December 14, 2017Inventors: YOU GE, Meng Kong Lye, Zhijie Wang
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Patent number: 9548255Abstract: An integrated circuit (IC) package has a base, side walls mechanically connected to the base, IC dies respectively mounted on inner surfaces of the side walls or the base, and electrical connections connecting a corresponding IC die to another component of the IC package. In one embodiment, each die is electrically connected to only bond pads on its corresponding side wall or base. Each such side wall and the base have routing structures (e.g., copper traces) that connect each bond pad to another component of the IC package. The IC package is assembled using a flexible substrate that has side regions that rotate relative to the base such that the routing structures do not break. By connecting an IC die only to bond pads on its corresponding side wall or base with bond wires, the bond wires will not break during side-wall rotation.Type: GrantFiled: April 27, 2016Date of Patent: January 17, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: You Ge, Meng Kong Lye, Zhijie Wang
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Publication number: 20170009387Abstract: A woven signal-routing substrate for a wearable electronic devoce has conductive warps and wefts that are woven with each other and with insulative warps and wefts. Woven electrical cross-connections are formed at some of the intersections of the conductive warps and wefts, while no electrical cross-connections are formed at other intersections, to provide a signal-routing architecture for the substrate that can be used to route signals between electronic components of the wearable device. Non-connecting intersections are formed using insulative warps that are sufficiently thicker than the relatively thin conductive warps to enable a conductive weft to cross a conductive warp without making physical contact at intersection locations where an electrical cross-connection is not desired. The woven electrical cross-connections may be formed at other intersection locations using weaving topologies that ensure that the corresponding mutually orthogonal warps and wefts do contact one another.Type: ApplicationFiled: January 6, 2016Publication date: January 12, 2017Inventors: You Ge, Meng Kong Lye, Zhijie Wang