Abstract: A timing controller suitable for receiving image data and a timing signal from a host system and outputting output data to a data driving circuit may include a scrambler configured to output scrambled image data by scrambling the image data; a pattern detection unit configured to calculate a first unbalanced pattern count as a count of unbalanced patterns included in the image data and a second unbalanced pattern count as a count of unbalanced patterns included in the scrambled image data; and an output data determination unit configured to determine output data by using the first unbalanced pattern count and the second unbalanced pattern count.

Abstract: A timing controller suitable for receiving image data and a timing signal from a host system and outputting output data to a data driving circuit may include a scrambler configured to output scrambled image data by scrambling the image data; a pattern detection unit configured to calculate a first unbalanced pattern count as a count of unbalanced patterns included in the image data and a second unbalanced pattern count as a count of unbalanced patterns included in the scrambled image data; and an output data determination unit configured to determine output data by using the first unbalanced pattern count and the second unbalanced pattern count.

Abstract: Provided are a source driver integrated circuit (IC) according to the present disclosure including a first buffer in which first sensing data transmitted from a first source driver IC is stored, a sensing data generation circuit configured to sense a characteristic of a driving element included in each pixel and generate second sensing data, a second buffer in which the second sensing data is stored, a control circuit configured to generate a selection signal in response to an operation command, and a selector configured to transmit one of the first sensing data stored in the first buffer and the second sensing data stored in the second buffer to a second source driver IC in response to the selection signal.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates of touch coordinates, a selection circuit configured to time-divide 1 frame duration, to output the X coordinate emission data to a display driving circuit during an X coordinate field, and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to output control data for allowing each pixel to emit light in units of data line groups including i data lines using the X coordinate emission data during the X coordinate field and for allowing each pixel to emit light in units of gate lines including j gate lines using the Y coordinate emission data during the Y coordinate field, to the display driving circuit.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates of the touch coordinates, a selection circuit configured to time-divide 1 frame duration, to output image data to a display driving circuit during a display field, to output the X coordinate emission data to the display driving circuit during an X coordinate field, and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to generate source control data and gate control data for outputting the image data, the X coordinate emission data, and the Y coordinate emission data to a display panel and to output the source control data and the gate control data to the display driving circuit.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates, a selection circuit configured to time-divide 1 frame duration to output the X coordinate emission data to a display driving circuit during an X coordinate field and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to output control data for allowing pixels connected to one data line to emit light in units of 1 data line using the X coordinate emission data during the X coordinate field and allowing pixels connected to one gate line to emit light in units of 1 gate line using the Y coordinate emission data during the Y coordinate field, to the display driving circuit.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for each data line group and Y coordinate emission data for each gate line group, a selection circuit configured to output the X coordinate emission data during an X coordinate field and to output the Y coordinate emission data during a Y coordinate field, and a control data generation circuit configured to output control data for allowing each pixel to emit light in units of the data line groups based on the X coordinate emission data during the X coordinate field and allowing each pixel to emit light in units of the gate line groups based on the Y coordinate emission data during the Y coordinate field, wherein the X coordinate emission data for each data line group and the Y coordinate emission data for each gate line group have random color.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for each data line group and Y coordinate emission data for each gate line group, a selection circuit configured to output the X coordinate emission data during an X coordinate field and to output the Y coordinate emission data during a Y coordinate field, and a control data generation circuit configured to output control data for allowing each pixel to emit light in units of the data line groups based on the X coordinate emission data during the X coordinate field and allowing each pixel to emit light in units of the gate line groups based on the Y coordinate emission data during the Y coordinate field, wherein the X coordinate emission data for each data line group and the Y coordinate emission data for each gate line group have random color.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates, a selection circuit configured to time-divide 1 frame duration to output the X coordinate emission data to a display driving circuit during an X coordinate field and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to output control data for allowing pixels connected to one data line to emit light in units of 1 data line using the X coordinate emission data during the X coordinate field and allowing pixels connected to one gate line to emit light in units of 1 gate line using the Y coordinate emission data during the Y coordinate field, to the display driving circuit.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates of touch coordinates, a selection circuit configured to time-divide 1 frame duration, to output the X coordinate emission data to a display driving circuit during an X coordinate field, and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to output control data for allowing each pixel to emit light in units of data line groups including i data lines using the X coordinate emission data during the X coordinate field and for allowing each pixel to emit light in units of gate lines including j gate lines using the Y coordinate emission data during the Y coordinate field, to the display driving circuit.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates of the touch coordinates, a selection circuit configured to time-divide 1 frame duration, to output image data to a display driving circuit during a display field, to output the X coordinate emission data to the display driving circuit during an X coordinate field, and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to generate source control data and gate control data for outputting the image data, the X coordinate emission data, and the Y coordinate emission data to a display panel and to output the source control data and the gate control data to the display driving circuit.

Abstract: Provided are a source driver integrated circuit (IC) according to the present disclosure including a first buffer in which first sensing data transmitted from a first source driver IC is stored, a sensing data generation circuit configured to sense a characteristic of a driving element included in each pixel and generate second sensing data, a second buffer in which the second sensing data is stored, a control circuit configured to generate a selection signal in response to an operation command, and a selector configured to transmit one of the first sensing data stored in the first buffer and the second sensing data stored in the second buffer to a second source driver IC in response to the selection signal.

Abstract: A light-emitting diode package includes a package body. The package body includes an upper insulation substrate including upper conductive patterns, a lower insulation substrate including lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes an upper via disposed in the upper insulation substrate, a lower via disposed in the lower insulation substrate, the upper via and the lower via not overlaid with each other.

Abstract: A light-emitting diode package includes a package body. The package body includes an upper insulation substrate including upper conductive patterns, a lower insulation substrate including lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes an upper via disposed in the upper insulation substrate, a lower via disposed in the lower insulation substrate, the upper via and the lower via not overlaid with each other.

Abstract: A light-emitting diode package includes a package body and a light-emitting diode chip disposed on the package body. The package body includes upper conductive patterns disposed on an upper insulation substrate, a lower insulation substrate disposed on lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes upper vias electrically connecting each of the upper conductive patterns to each of the middle conductive patterns, respectively, the upper vias being disposed in the upper insulation substrate, and lower vias electrically connecting each of the middle conductive patterns to each of the lower conductive patterns, respectively, the lower vias disposed in the lower insulation substrate.

Abstract: A light-emitting diode package includes a package body and a light-emitting diode chip disposed on the package body. The package body includes upper conductive patterns disposed on an upper insulation substrate, a lower insulation substrate disposed on lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes upper vias electrically connecting each of the upper conductive patterns to each of the middle conductive patterns, respectively, the upper vias being disposed in the upper insulation substrate, and lower vias electrically connecting each of the middle conductive patterns to each of the lower conductive patterns, respectively, the lower vias disposed in the lower insulation substrate.

Abstract: A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes.

Abstract: A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes.

Abstract: A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes.

Abstract: A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes.