Patents by Inventor You-Jiun Wang

You-Jiun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LVS implementation for FinFET design
    Patent number: 8631382
    Abstract: A method includes converting an active region in a layout of an integrated circuit into a fin-based structure that has a fin. The active region belongs to an integrated circuit device, and has a planar layout structure. The method further includes extracting a Resistance-Capacitance (RC) loading of the integrated circuit device using the parameters of the fin-based structure. The steps of converting and extracting are performed by a computer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Jiun Wang, Kai-Ming Liu
  • LVS Implementation for FinFET Design
    Publication number: 20130239077
    Abstract: A method includes converting an active region in a layout of an integrated circuit into a fin-based structure that has a fin. The active region belongs to an integrated circuit device, and has a planar layout structure. The method further includes extracting a Resistance-Capacitance (RC) loading of the integrated circuit device using the parameters of the fin-based structure. The steps of converting and extracting are performed by a computer.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Jiun Wang, Kai-Ming Liu
  • Method of transforming serial scrambler to parallel scrambler, parallel scrambler and double-edge-triggered register with XOR operation
    Patent number: 7639801
    Abstract: A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ? ( x ) = ? q = 0 N ? c q ? x q ? ? or ? ? b ? ( i ) = ? q = 1 N ? c q ? b ? ( i - q ) . The method first determines a transformation formula: b ? ( kN + i ) = ? q = 1 N ? c q ? b ? ( ( k - R ) ? N + i + R ? ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M?2, bMj+M?1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 29, 2009
    Assignee: National Central University
    Inventors: Shyh-Jye Jou, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, Chih-Hsien Lin
  • Method of transforming serial scrambler to parallel scrambler, parallel scrambler and double-edge-triggered register with XOR operation
    Publication number: 20060029225
    Abstract: A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ? ( x ) = ? q = 0 N ? c q ? x q ? ? ? or ? ? ? b ? ( i ) = ? q = 1 N ? c q ? b ? ( i - q ) . The method first determines a transformation formula: b ? ( kN + i ) = ? q = 1 N ? c q ? b ? ( ( k - R ) ? N + i + R ? ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M?2, bMj+M?1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula.
    Type: Application
    Filed: March 31, 2005
    Publication date: February 9, 2006
    Inventors: Shyh-Jye Jou, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, Chih-Hsien Lin