Abstract: A non-volatile semiconductor memory device, including a memory array having a plurality of first bit line groups and a plurality of second bit line groups that are alternately arranged to be adjacent each other, a plurality of data lines, a plurality of first page buffers, a plurality of second page buffers, and a plurality of switches. Each of the first page buffers is electrically connected to a corresponding one of the first bit line groups and arranged on a first side of the memory array. The first page buffers transmit data to the data lines. Each of the second page buffers is electrically connected to a corresponding one of the second bit line groups and arranged on a second side of the memory array. Each of the switches enables data transmission between a corresponding one of the first page buffers and a corresponding one of the second page buffers.

Abstract: Disclosed herein is a horn switch assembly for vehicles. The horn switch assembly comprising studs, elastic members, a horn plate, a movable switch terminal, and a stationary switch terminal, is disposed between an airbag housing mounted in a steering wheel and an airbag cover vertically slidably attached to the airbag housing. Each of the elastic members has a relatively small spring constant since the elastic members of the horn switch assembly support only the airbag cover formed of a plastic material easily broken when an airbag is expanded, whereby the elastic members and the studs are miniaturized, and the force necessary to manipulate the horn switch assembly is reduced.

Abstract: A delay circuit, e.g., for a semiconductor device, having a plurality of cascade-connected stages that successively delay an input signal, may include: plural cascaded-connected delay devices representing instances of a first type of delay unit corresponding to the stages, respectively; plural resistance units coupled between a node having a source voltage of varying magnitude Vvar and odd-numbered ones of the delay devices, respectively; and plural capacitance units coupled between a node having another voltage Vuni of substantially uniform magnitude relative to Vvar and nodes representing the outputs of the odd-numbered delay devices; where corresponding ones of the plurality of capacitor units and the plurality of resistance units represent instances, respectively, of a second type of delay unit.