Patents by Inventor You Min JI

You Min JI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854659
    Abstract: A memory system and a method of operating the memory system are provided. The memory system may determine, on a determination that the memory system enters thermal throttling mode, a target status read check period based on threshold voltage distribution offset for the target memory die, and set a timer to transmit a status read command for the target memory die to the memory device based on the target status read check period.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventors: Da Seul Lee, Seon Ju Lee, You Min Ji
  • Publication number: 20230075808
    Abstract: A memory system and a method of operating the memory system are provided. The memory system may determine, on a determination that the memory system enters thermal throttling mode, a target status read check period based on threshold voltage distribution offset for the target memory die, and set a timer to transmit a status read command for the target memory die to the memory device based on the target status read check period.
    Type: Application
    Filed: March 3, 2022
    Publication date: March 9, 2023
    Inventors: Da Seul LEE, Seon Ju LEE, You Min JI
  • Patent number: 11238926
    Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: You Min Ji, Keun Woo Lee
  • Patent number: 11194687
    Abstract: Provided is a controller for controlling a memory device. The controller may include a media scanner suitable for performing a media scan operation of reading a predetermined size of data from the memory device in a predetermined cycle, detecting an error of the read data, generating corrected data of the read data, and storing the corrected data in the memory device, a period calculator suitable for calculating a power-off period, and a media scan controller suitable for changing the predetermined cycle according to the power-off period.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: You-Min Ji, Bum-Ho Kim
  • Publication number: 20200210303
    Abstract: Provided is a controller for controlling a memory device. The controller may include a media scanner suitable for performing a media scan operation of reading a predetermined size of data from the memory device in a predetermined cycle, detecting an error of the read data, generating corrected data of the read data, and storing the corrected data in the memory device, a period calculator suitable for calculating a power-off period, and a media scan controller suitable for changing the predetermined cycle according to the power-off period.
    Type: Application
    Filed: November 1, 2019
    Publication date: July 2, 2020
    Inventors: You-Min JI, Bum-Ho KIM
  • Publication number: 20200168272
    Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.
    Type: Application
    Filed: July 16, 2019
    Publication date: May 28, 2020
    Inventors: You Min JI, Keun Woo LEE