Abstract: A measurement device for measuring a blood pressure is provided. The measurement device includes a first sensor, a processor, and a measurement component. The first sensor is used to generate a first sensing signal. The processor receives the first sensing signal and determines whether an event occurs according to the first sensing signal. The measurement component is enabled to measure the blood pressure. When the processor determines that the event occurs, the processor triggers a reminding operation related to enabling of the measurement component.

Abstract: The present disclosure provides a sensor module for simultaneously measuring electrocardiography (ECG) and pulse signal of an object, including: a first electrode having a first surface and an opposite, second surface; a deformable contact sensor having a first surface and an opposite, second surface, wherein the first surfaces of the first electrode and the deformable contact sensor are configured to face toward a region to be measured of the object; a compressible material disposed on at least one of the second surfaces of the first electrode and the deformable contact sensor; and a second electrode operatively connected to the first electrode.

Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.

Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Abstract: A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be in a worst-case situation if analyzed by using static timing analysis can be selected from a number of possible clock signals by using a simple determination process. The selected set of clock signals are then employed in static timing analysis on the logic circuit to verify whether no timing violation occurs on each signal transmission path of the logic circuit. If not, it indicates that the logic circuit using any selection of the possible clock signals will not cause timing violation thereon. Thus, the static timing analysis can be accomplished efficiently.

Abstract: The design flow method of the present invention accurately performs timing analysis during the circuit design stage, so that the DFT synthesis procedure can effectively control the timing information, preventing timing violation from happening during the IC design flow process. Furthermore, the information of the CTS procedure and the static-timing analysis procedure is combined to perform accurate timing estimation.

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.

Abstract: A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.

Abstract: A method for scheduling execution sequence of read and write operations is disclosed, which is used for controlling the read and write operations between a first device and a second device. First, if there are more than two write operations waiting to be executed, the write operations are executed only after the completion of all of the read operations. If there are no more than two write operations waiting to be executed and there are read operations waiting to be executed, all of the read operations are to be executed when the read operation to be executed is associated with a data address different from the data address associated with the write operation next to the read operation. After all of the read operations are executed, the write operations are to be executed.

Abstract: A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

Abstract: A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.

Abstract: The design flow method of the present invention accurately performs timing analysis during the circuit design stage, so that the DFT synthesis procedure can effectively control the timing information, preventing timing violation from happening during the IC design flow process. Furthermore, the information of the CTS procedure and the static-timing analysis procedure is combined to perform accurate timing estimation.

Abstract: A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be in a worst-case situation if analyzed by using static timing analysis can be selected from a number of possible clock signals by using a simple determination process. The selected set of clock signals are then employed in static timing analysis on the logic circuit to verify whether no timing violation occurs on each signal transmission path of the logic circuit. If not, it indicates that the logic circuit using any selection of the possible clock signals will not cause timing violation thereon.

Abstract: A signal converting device and method for converting signals from memory interfaces into main system interfaces. The present invention can completely convert response signals from high frequency devices into low frequency devices, for solving low efficient and disadvantages caused by asynchronous conversion. The signal loss is not occurred when the signal converting device is in pseudo synchronization. By applying the present invention, the computer system can work normally and rapidly, in which the frequency of the request signals from the main system interface is higher than half of the frequency of the response signals from the memory interface. The compurter system is, for example computer system for 100 MHz/133 MHz or 66 MHz/100 MHz.

Abstract: A static timing analysis method on a circuit using generated clock, so as to solve the issues that the conventional static timing analysis cannot be performed on the circuit of flip-flop and the latch using generated clock. By the method of the invention, the user can promptly known whether or not the signal path with respect to the flip-flop and latch has timing violation, whereby the correctness of the clock used in the circuit can be judged.