Abstract: A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract: A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.

Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

Abstract: A chip with tri-layer electrodes and micro-cavity arrays for control of bioparticles and a manufacturing method thereof are revealed. The chip captures and releases bioparticles into and from preset cavities by dielectrophoresis (DEP) force generated by electrodes. The chip includes an upper layer body, a middle layer body, a lower layer body, respectively disposed with an electrode, and micro flow chambers. The electrodes of the upper layer body and the middle layer body are common electrodes while the electrode of the lower layer body is a dispersive electrode array exposed on the bottom of lower-layer microcavity. The cell capture and release at the single-cell level and the cell population level are attained by application of an AC electric field.

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract: A chip with tri-layer electrodes and micro-cavity arrays for control of bioparticles and a manufacturing method thereof are revealed. The chip captures and releases bioparticles into and from preset cavities by dielectrophoresis (DEP) force generated by electrodes. The chip includes an upper layer body, a middle layer body, a lower layer body, respectively disposed with an electrode, and micro flow chambers. The electrodes of the upper layer body and the middle layer body are common electrodes while the electrode of the lower layer body is a dispersive electrode array exposed on the bottom of lower-layer microcavity. The cell capture and release at the single-cell level and the cell population level are attained by application of an AC electric field.