Abstract: A computing system with graphics processor boosting is shown. The computing system has a graphics processing unit controlling a display, a code memory storing instructions, and a processor operating the graphics processing unit to control the display. The processor is configured to execute the instructions retrieved from the code memory to implement a plurality of graphics processor boosting modules for the graphics processing unit, and implement an activation controller that controls activation of the different graphics processor boosting modules through different configuration interfaces with balances between the different graphics processor boosting modules.

Abstract: A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.

Abstract: A method for performing automatic activation control regarding VRS and associated apparatus are provided. The method applicable to a processing circuit may include: utilizing a rendering classifier to intercept at least one set of original graphic commands on a command path to obtain at least one rendering property, for classifying rendering corresponding to the at least one set of original graphic commands; utilizing the rendering classifier to classify the rendering into at least one predetermined rendering type among multiple predetermined rendering types according to the at least one rendering property, in order to determine at least one shading rate corresponding to the at least one predetermined rendering type for the rendering; and utilizing a shading rate controller to control the processing circuit to selectively activate a VRS function of the processing circuit, for rendering at the at least one shading rate corresponding to the at least one predetermined rendering type.

Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium, are provided. The method for processing graphics data with a graphics rendering pipeline comprising a mesh shader and a tiler, comprising outputting, by the mesh shader in response to an input of the graphics data, legacy mesh shader output parameters including vertices and primitives, and additional data with a meshlet bounding-box, or axis-aligned bounding box (AABB) structure; sending the AABB to the tiler as an input, and generating, by the tiler, a visibility stream according to the AABB, wherein each entity of the visibility stream indicates that the AABB is fully visible, partially visible, or invisible in the view frustum; and sending the visibility stream back to the tiler as a further input along with the legacy mesh shader output parameters for coming rasterization in a fragment pass.

Abstract: An application programming interface includes a mesh shader, a rasterizer, and a fragment shader. The mesh shader is used to process 3-dimensional objects and output vertices, primitives, and a plurality of bounding volumes of the 3-dimensional objects. The rasterizer is linked to the mesh shader, and used to project the vertices, the primitives, and the plurality of bounding volumes into 2-dimensional fragments. The fragment shader is linked to the rasterizer, and used to output a 2-dimensional image according to the 2-dimensional fragments.

Abstract: A computing system performs artificial-intelligence (AI) super-resolution (SR). The computing system includes multiple processors, which further includes a graphics processing unit (GPU) and an AI processing unit (APU). The computing system also includes a memory to store AI models. When detecting an indication that the loading of the GPU exceeds a threshold, the processors reduce the resolution of a video output from the GPU in response to the indication. One of the AI models is selected based on graphics scenes in the video and the respective power consumption estimates of the AI models. The processors then perform AI SR operations on the video using the selected AI model to restore the resolution of the video for display.

Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.

Abstract: An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one metal layer. The power mesh has a specific area corresponding to a specific functional circuit block of the functional circuit blocks. The specific area at least has a first power trunk of a first power source and a second power trunk of a second power source distributed therein.

Abstract: A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a dynamic configurable cache and a plurality of cores/processors by rejecting a request from any of the cores/processors during a bus freeze period, wherein the dynamic configurable cache is implemented with an on-chip memory; and adjusting a size of a portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for one of the cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: The present invention provides a processing system and associated method; the processing system includes a processing unit, a peripheral unit consuming system resource, a support unit capable of providing the system resource, a buffer capable of storing a portion of the system resource, and a system power manager (SPM). When the processing unit suspends for idle, the peripheral unit consumes the buffer and thus does not need system resource from the support unit, so the support unit and/or the corresponding system resource can be powered down. When the buffer is consumed, the SPM is capable of allocating the system resource for the peripheral unit in response to request of the peripheral unit, so the processing unit does not have to leave idle for allocating the system resource.

Abstract: A graphic processing unit (GPU) with a configurable filtering module (CFU) and an operation method thereof are presented. The graphic processing unit comprises a memory module and a configurable filtering module. The memory module stores at least one texture image. The configurable filtering module, connected to the memory module, comprises a plurality of filter equations, from which a filter equation is selected. A plurality of pixel points are sampled from the texture image. Each sampled pixel point is set with a weight value respectively. Each sampled pixel point with a weight value corresponding thereto is substituted into the selected filter equation to perform an operational process to acquire an operated value. Thereby, the user can decide the operation method of the GPU by selecting an appropriate filter equation and setting adjustable parameters in the filter equation.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a dynamic configurable cache and a plurality of cores/processors by rejecting a request from any of the cores/processors during a bus freeze period, wherein the dynamic configurable cache is implemented with an on-chip memory; and adjusting a size of a portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for one of the cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number (N) of stream processing units, and the memory module is configured with a number (N) of memory bank units each corresponding to a respective one of the stream processing units. The memory module is reconfigurable based on a desired inter-level configuration so that each of the memory bank units is configured to have a memory size sufficient to meet processing requirement of the respective one of the stream processing units.

Abstract: A graphic processing unit (GPU) with a configurable filtering module (CFU) and an operation method thereof are presented. The graphic processing unit comprises a memory module and a configurable filtering module. The memory module stores at least one texture image. The configurable filtering module, connected to the memory module, comprises a plurality of filter equations, from which a filter equation is selected. A plurality of pixel points are sampled from the texture image. Each sampled pixel point is set with a weight value respectively. Each sampled pixel point with a weight value corresponding thereto is substituted into the selected filter equation to perform an operational process to acquire an operated value. Thereby, the user can decide the operation method of the GPU by selecting an appropriate filter equation and setting adjustable parameters in the filter equation.

Abstract: In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N?2. When the scheduler receives a stream element from a Pth stream fetching unit, the scheduler assigns a Pth stream processing unit as a target stream processing unit when the Pth stream processing unit does not encounter a bottleneck condition, assigns a Qth stream processing unit, which does not encounter the bottleneck condition, as the target stream processing unit when the Pth stream processing unit encounters the bottleneck condition, where 1?P?N, 1?Q?N, and P?Q, and dispatches the received stream element to the target stream processing unit such that the target stream processing unit processes the stream element dispatched from the scheduler.

Abstract: A method for performing image signal processing (ISP) with the aid of a graphics processing unit (GPU) includes: utilizing an ISP pipeline to perform pre-processing on source data of at least one portion of at least one source frame image to generate intermediate data of at least one portion of at least one intermediate frame image, where the ISP pipeline stores the intermediate data into a memory; and utilizing the GPU to retrieve the intermediate data from the memory and perform specific processing on the intermediate data to generate processed data, where the GPU stores the processed data into the external/on-chip memory. In particular, at least one of the intermediate data and the processed data complies with a specific color format. In addition, an associated apparatus is further provided.