Abstract: An array substrate comprises a base substrate, a light-shielding layer disposed on the base substrate, and a plurality of transistors disposed in an array on a side of the light-shielding layer away from the base substrate. The light-shielding layer comprises a plurality of light-shielding portions. Orthographic projections of a source terminal of each of the transistors and a drain terminal of one adjacent transistor in a same row on the base substrate are located on one same light-shielding portion, and orthographic projections of a source terminal and a drain terminal of one same transistor on the base substrate are respectively located on two adjacent light-shielding portions that are spaced apart. A display panel comprises the array substrate.

Abstract: A gate driving circuit and a display panel are provided. A gate driving unit in the gate driving circuit includes a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to the pull-up node. The pull-down control module is electrically connected to the pull-down node. The pull-down control module is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit. The pull-down module is electrically connected to the pull-up node and the pull-down node.

Abstract: A display panel, for displaying images including a first frame and a second frame, includes subpixels, scan lines, data lines, and a compensation module. The data lines are configured to input a first data voltage to the subpixels in a display period of the first frame and to input a second data voltage to the subpixels in a display period of the second frame. The compensation module is configured to input a first compensation voltage to the subpixels in a blank period of the first frame and to input a second compensation voltage to the subpixels in a blank period of the second frame, where the first compensation voltage is not zero, and the second compensation voltage is not zero.

Abstract: The present disclosure provides a gate driver on array (GOA) circuit including a plurality of GOA units disposed in N-stage cascade, and an nth-stage GOA unit includes a node control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a stop control module, wherein 1<n<N?1, and both the n and the N are positive integers.

Abstract: A gate driving circuit and a display panel are provided. A gate driving unit in the gate driving circuit includes a pull-up control module, a pull-up node, a pull-down control module, a pull-down node, and a pull-down module. The pull-up control module is electrically connected to the pull-up node. The pull-down control module is electrically connected to the pull-down node. The pull-down control module is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit. The pull-down module is electrically connected to the pull-up node and the pull-down node.

Abstract: The present disclosure discloses a display panel and a display device. The compensation module in the display panel is configured to input a first compensation voltage to a subpixel in the blank period of the first frame and a second compensation voltage to the subpixel in the blank period of the second frame. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. The first compensation voltage is not zero, and the second compensation voltage is not zero.

Abstract: The present disclosure discloses a display panel and a display device. The compensation module in the display panel is configured to input a first compensation voltage to a subpixel in the blank period of the first frame and a second compensation voltage to the subpixel in the blank period of the second frame. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. The first compensation voltage is not zero, and the second compensation voltage is not zero.

Abstract: The present disclosure provides a gate driver on array (GOA) circuit including a plurality of GOA units disposed in N-stage cascade, and an nth-stage GOA unit includes a node control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a stop control module, wherein 1<n<N?1, and both the n and the N are positive integers.

Abstract: A Gate Driver on Array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. An Nth stage GOA unit includes a pull-up control circuit, a pull-up output circuit and a scan direction control circuit. The scan direction control circuit can be controlled by the clock signal to realize the alternating forward and backward scanning. The output terminal of the scan direction control circuit is connected with the output terminal of the pull-up control circuit, and the output terminal potential of the pull-up control circuit can be alternately changed.

Abstract: The present embodiment provides a GOA circuit and a display panel, in which the GOA circuit comprises a forward/backward scanning control module, an output module, a potential regulation module, a node control module, and a voltage stabilizer module. A first node and a third node are not conducted when a second node is at a second potential; the first node and the third node are conducted and have a second potential when the second node is at a third potential, wherein the second potential is opposite to the third potential. Thus, GOA circuit's leakage issue existing in the TP suspension stage can be improved.

Abstract: The present application discloses a display panel and a display device. The display panel includes a non-display region and a gate driver on array (GOA) unit region in the non-display region. The GOA unit region includes multi-level GOA units arranged in multiple columns, thereby improving a space limitation problem associated with arranging a plurality of GOA units in a display panel while the display panel achieves high resolution.

Abstract: A Gate Driver on Array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. An Nth stage GOA unit includes a pull-up control circuit, a pull-up output circuit and a scan direction control circuit. The scan direction control circuit can be controlled by the clock signal to realize the alternating forward and backward scanning. The output terminal of the scan direction control circuit is connected with the output terminal of the pull-up control circuit, and the output terminal potential of the pull-up control circuit can be alternately changed.

Abstract: The present embodiment provides a GOA circuit and a display panel, in which the GOA circuit comprises a forward/backward scanning control module, an output module, a potential regulation module, a node control module, and a voltage stabilizer module. A first node and a third node are not conducted when a second node is at a second potential; the first node and the third node are conducted and have a second potential when the second node is at a third potential, wherein the second potential is opposite to the third potential. Thus, GOA circuit's leakage issue existing in the TP suspension stage can be improved.

Abstract: An array substrate comprises a base substrate, a light-shielding layer disposed on the base substrate, and a plurality of transistors disposed in an array on a side of the light-shielding layer away from the base substrate. The light-shielding layer comprises a plurality of light-shielding portions. Orthographic projections of a source terminal of each of the transistors and a drain terminal of one adjacent transistor in a same row on the base substrate are located on one same light-shielding portion, and orthographic projections of a source terminal and a drain terminal of one same transistor on the base substrate are respectively located on two adjacent light-shielding portions that are spaced apart. A display panel comprises the array substrate.

Abstract: The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

Abstract: A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.

Abstract: The present application discloses a display panel and a display device. The display panel includes a non-display region and a gate driver on array (GOA) unit region in the non-display region. The GOA unit region includes multilevel GOA units arranged in multiple columns, thereby improving a space limitation problem associated with arranging a plurality of GOA units in a display panel while the display panel achieves high resolution.

Abstract: A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.

Abstract: The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

Abstract: The present invention relates to a new method of producing functionally active recombinant porcine Intrinsic Factor as well as the protein (i.e., porcine Intrinsic Factor) produced thereby. In particular, the vector comprising the DNA encoding the protein is introduced into a Chinese Hamster Ovary (CHO) host cell under conditions sufficient for optimal expression of functional protein. The expressed protein may then be subjected to three methods ultimately resulting in a protein having at least 97% purity.