Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

Abstract: A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter.

Abstract: In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.

Abstract: A method for simulating large circuits in full-scale. To enhance the simulation efficiency, subcircuits are extracted from a circuit and thence a hierarchical structure is established using the extracted subcircuits. Subsequently, the circuit is partitioned and a current-voltage table for each subcircuit is dynamically generated. A transient analysis of the circuit is preformed at each incremental time step and a recursive latency check is preformed from the top to the bottom level of the hierarchical structure to determine the active part of the circuit. Using the current-voltage curves, a portion of the conductance matrix corresponding to the active part is rebuild at each incremental time step, which significantly reduces the simulation time.

Abstract: A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter.

Abstract: In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.

Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

Abstract: In accordance with the present invention there is provided a method of simulating a memory circuit design in order to verify the signal strength of bit lines. The method begins by identifying circuit elements of the memory circuit design. Next, a memory circuit path is extracted from the circuit elements. The memory circuit is simulated and the maximum voltage difference between bit lines is measured. The maximum voltage difference is measured to a noise margin in order to verify the signal strength of the bit lines.

Abstract: There is provided a method of performing a timing soft error check on a simulated circuit. The method comprises creating a critical-path circuit or using a full-chip circuit to be analyzed of the circuit. Next, the circuit is simulated based on an initial minimum optimization parameter and an initial maximum optimization parameter. A maximum and minimum primary criterion parameter are calculated for each of the minimum and maximum optimization parameters. If the minimum and maximum optimization parameters do not indicate the same status (i.e., both succeed or both fail), then a new current optimization parameter is determined. The circuit is then simulated using the new current optimization parameter. If the simulation is successful, then a timing soft error check is performed. If the simulation is not successful, then it is determined if the primary criterion parameter is converging. If the primary criterion parameter is not converging, then the current optimization parameter is set to a new value.

Abstract: A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.

Abstract: An automatic memory characterization system for determining timing characteristics associated with each of a plurality of circuit instances of a memory compiler circuit design includes: an automatic circuit reduction tool for receiving a circuit netlist extracted from layout data defining a circuit instance of the memory compiler, and for generating a critical path netlist; a memory storage unit for storing a timing parameter database including a script file having memory characterization instructions, and at least one specification file associated with one of the timing characteristics to be characterized for the circuit instance, the specification file having a plurality of input signal parameters defining a plurality of input signals to be applied to selected input nodes of the circuit instance, and a plurality of output loading parameters defining a plurality of output loads to be applied to selected output nodes of the circuit instance; a stimulus generator responsive to the input signal parameters and o

Abstract: A method for identifying and selecting pertinent subcircuits from a given circuit design for generating simulation results representative of the given circuit design is disclosed. A large circuit design having a number of input pins and output pins, and one or more clock pins can be simulated by a number of subcircuits where each subcircuit is comprised of circuit information from an input pin to one or more latch devices, an output pin to one or more latch devices, or an output pin to one or more input pins. A latch device can be a flip-flop.