Abstract: A method and an apparatus which adjusts a signal read from an optical disc in order to obtain stable binary data. The signal adjustment method comprises (a) detecting a period of an input signal of a predetermined code; (b) determining whether the detected period is smaller than a predetermined value; and (c) if the detected period is determined to be smaller than the predetermined value, adjusting the input signal so that its period equals the predetermined value, and outputting the input signal. The signal adjustment method and apparatus of the present invention reduce errors and improve system performance, when a signal input to the binary processor does not meet its code feature.

Abstract: A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An?1An?2 . . . A1A0 and a second binary data Bn?1Bn?2 . . . B1B0, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation: F(A?B)=A(n?1)?·B(n?1)+(A(n?1)?+B(n?1))·{A(n?2)?·B(n?2)+(A(n?2)?+B(n?2)) . . . {A1?·B1+(A1?+B1)·(A0?+B0)}} where subscripts denote a position of a bit of the N-bit binary data and a prime (?) indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.

Abstract: A clock generator for reproducing data recorded onto an optical disk, and more particularly, an apparatus for stably generating a clock signal synchronized with an input signal and a method of generating a clock signal. The apparatus generating a clock signal includes a voltage controlled oscillator, a phase compensator, a frequency compensator, and an adder. The voltage controlled oscillator generates a clock signal of a frequency that varies with a control voltage signal. The phase compensator receives an input signal and the clock signal, detects a phase difference between the input signal and the clock signal, and generates a first control voltage corresponding to the phase difference. The frequency compensator receives the input signal and the clock signal, detects a frequency difference between the input signal and the clock signal, and generates a second control voltage corresponding to the frequency difference.

Abstract: A method and an apparatus which adjusts a signal read from an optical disc in order to obtain stable binary data. The signal adjustment method comprises (a) detecting a period of an input signal of a predetermined code; (b) determining whether the detected period is smaller than a predetermined value; and (c) if the detected period is determined to be smaller than the predetermined value, adjusting the input signal so that its period equals the predetermined value, and outputting the input signal. The signal adjustment method and apparatus of the present invention reduce errors and improve system performance, when a signal input to the binary processor does not meet its code feature.

Abstract: A clock generator for reproducing data recorded onto an optical disk, and more particularly, an apparatus for stably generating a clock signal synchronized with an input signal and a method of generating a clock signal. The apparatus generating a clock signal includes a voltage controlled oscillator, a phase compensator, a frequency compensator, and an adder. The voltage controlled oscillator generates a clock signal of a frequency that varies with a control voltage signal. The phase compensator receives an input signal and the clock signal, detects a phase difference between the input signal and the clock signal, and generates a first control voltage corresponding to the phase difference. The frequency compensator receives the input signal and the clock signal, detects a frequency difference between the input signal and the clock signal, and generates a second control voltage corresponding to the frequency difference.

Abstract: A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An−1An−2 . . . A1A0 and a second binary data Bn−1Bn−2 . . .