Patents by Inventor You-Ren Liu
You-Ren Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8716802Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: GrantFiled: August 9, 2010Date of Patent: May 6, 2014Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Patent number: 8477475Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.Type: GrantFiled: August 4, 2011Date of Patent: July 2, 2013Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Publication number: 20110292565Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.Type: ApplicationFiled: August 4, 2011Publication date: December 1, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Patent number: 8027144Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.Type: GrantFiled: April 28, 2009Date of Patent: September 27, 2011Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Publication number: 20100320540Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: ApplicationFiled: August 9, 2010Publication date: December 23, 2010Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Publication number: 20100271750Abstract: A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes.Type: ApplicationFiled: April 28, 2009Publication date: October 28, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Ling Chiu, Victor Chiang Liang, Chih-Yu Tseng, Hui-Sheng Chang, Chia-Te Chien, You-Ren Liu
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Patent number: 7803687Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.Type: GrantFiled: October 17, 2008Date of Patent: September 28, 2010Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Patent number: 7804154Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: GrantFiled: December 11, 2008Date of Patent: September 28, 2010Assignee: United Microelectronics Corp.Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor Chiang Liang, You-Ren Liu, Chih-Chen Hsueh
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Publication number: 20100148263Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.Type: ApplicationFiled: December 11, 2008Publication date: June 17, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: KAI-LING CHIU, CHIH-YU TSENG, VICTOR CHIANG LIANG, YOU-REN LIU, Chih-Chen Hsueh
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Publication number: 20100099229Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.Type: ApplicationFiled: October 17, 2008Publication date: April 22, 2010Inventors: Kai-Ling Chiu, Chih-Yu Tseng, Victor-Chiang Liang, You-Ren Liu, Chih-Chen Hsueh