Abstract: An SRAM device comprising a memory cell, the memory cell comprising two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, and wherein a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing such that the threshold voltage on the logic signal input gates of the transistors is set at low level, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation such that the threshold voltage on the logic signal input gates of the transistors is set at high level.