Abstract: Embodiments of the disclosure provide a circuit for online adaptive direct current offset correction, which includes: an analog adder circuit, a digital-to-analog conversion circuit, a direct current detection circuit, an adaptive update signal generating circuit, an output circuit, and a mode selection circuit. Embodiments of the present disclosure also provide a zero-IF receiver including a circuit for online adaptive DC offset correction.

Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.

Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.

Abstract: The present invention provides a device and method for correcting error estimation of an analog-to-digital converter.

Abstract: A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimat

Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Abstract: There is disclosed a noise suppression device capable of improving the noise suppression accuracy while reducing the audio distortion. In this device, a suppression unit suppresses a noise component from the audio power spectrum by using the detection result of the audio-existing band and the noise band in the audio power spectrum including the noise component. A pitch harmonic structure extracting unit (105) extracts a pitch harmonic power spectrum from the audio power spectrum. An audio-existence judgment unit (106) judges whether the audio power spectrum has audio existence according to the extracted pitch harmonic power spectrum. A pitch harmonic structure repair unit (108) repairs the extracted pitch harmonic power spectrum.

Abstract: A band division noise suppressor suppressing noise sufficiently with a small amount of processing and a little voice distortion. In the band division noise suppressor, a band dividing section (101) divides an input voice signal into a low band voice signal and a high band voice signal. The low band voice signal is subjected to decimate at a decimation section (102), subjected to noise suppression at a low band noise suppressing section (103), and then interpolated at an interpolation section (104). On the other hand, the high band voice signal is subjected to noise suppression at a high band noise suppressing section (105). A band combination section (106) composes the bands of low-band and high-band voice signals subjected to noise suppression and outputs a voice signal subjected to noise suppression over the entire band.

Abstract: A pitch frequency estimation device capable of estimating a pitch frequency precisely while reducing the computational complexity required for the estimation of the pitch frequency. In this device, a spectrum extraction unit (104) extracts a pitch-harmonized spectrum from a voice spectrum. A spectral average calculation unit (106) calculates the average of the power of the pitch-harmonized spectra extracted by the spectrum extraction unit (104), in a manner to individually correspond to a plurality of pitch frequency candidates. An estimation unit estimates the pitch frequency by using the average valve calculated by the spectral average calculation unit (106).

Abstract: A speech processing apparatus and method may identify divisions of a signal spectrum as having a speech component or having no speech component. A comb filter is generated, based on a high-accuracy speech pitch obtained in the identified speech component divisions, for enhancing speech information in the speech component divisions. The comb filter is applied to the speech component divisions to suppress noise.

Abstract: Speech-non-speech identifying section 106 determines a speech spectral signal as a speech portion including a speech component in the case where a difference between the speech spectral signal and a value of a noise base is not less than a predetermined threshold, while determining the signal as a non-speech portion including only a noise and no speech component in the other case. Based on the presence or absence of a speech component in each frequency bin, comb filter generating section 107 generates a comb filter for enhancing a speech pitch. Attenuation coefficient calculating section 108 multiplies the comb filter by an attenuation coefficient based on frequency characteristics, sets an attenuation coefficient of an input signal for each frequency component, and outputs the attenuation coefficient of each frequency component to multiplying section 109. Multiplying section 109 multiplies a speech spectrum by the attenuation coefficient per frequency component basis.