Abstract: A method and an apparatus for determining a product manufacturing program, a device and a storage medium are provided. According to an information identifier configured for describing target key information of the product manufacturing requirement of the target user, a first product manufacturing program with the same information identifier as the target key information is determined from a product manufacturing program library; an operating parameter of a product manufacturing device when manufacturing the target product is input into the first product manufacturing program to simulate manufacturing of the target product, to obtain a first product parameter of a first product obtained, and the first product parameter is compared with a standard product parameter to obtain a first comparison result; when the first product parameter is same as the standard product parameter, the first product manufacturing program is determined as a first target product manufacturing program.

Abstract: Provided are method, apparatus, electronic device and storage medium for determining defect shape of wafer, wherein the method includes: for a target wafer image of each specification, comparing the target wafer image with the standard wafer image of this specification, and acquiring a coordinate position where each of defect points is located in the target wafer image; according to each coordinate position, projecting each of the defect points into the image to be classified of the target specification on the basis of the preset scaling ratio; determining target points where distance between any two adjacent points in the image to be classified is less than the preset distance; and determining the shape of the region formed by the target points, so as to determine the shape as the defect shape of the target wafer.

Abstract: A wafer chip testing method and apparatus, an electronic device and a storage medium are provided. The testing method includes: comparing each configuration parameter of each wafer chip with a standard specification threshold interval of a corresponding parameter type, and marking as marked test parameters configuration parameters which do not belong to the standard specification threshold intervals; and inputting all marked test parameters of individual wafer chip into a combination rule judgment function respectively, outputting wafer chip(s) which does not conform to any one or more rules in the combination rule judgment function, and determining the wafer chip(s) as unqualified wafer chip(s).

Abstract: A hardware neural network conversion method, a computing device, a compiling method and a neural network software and hardware collaboration system for converting a neural network application into a hardware neural network fulfilling a hardware constraint condition are disclosed. The method comprises: obtaining a neural network connection diagram corresponding to the neural network application; splitting the neural network connection diagram into neural network basic units; converting each of the neural network basic units so as to form a network having equivalent functions thereto and formed by connecting basic module virtual entities of neural network hardware; and connecting the obtained basic unit hardware network according to the sequence of splitting so as to create a parameter file for the hardware neural network. The present disclosure provides a novel neural network and a brain-like computing software and hardware system.

Abstract: A hardware neural network conversion method, a computing device, a compiling method and a neural network software and hardware collaboration system for converting a neural network application into a hardware neural network fulfilling a hardware constraint condition are disclosed. The method comprises: obtaining a neural network connection diagram corresponding to the neural network application; splitting the neural network connection diagram into neural network basic units; converting each of the neural network basic units so as to form a network having equivalent functions thereto and formed by connecting basic module virtual entities of neural network hardware; and connecting the obtained basic unit hardware network according to the sequence of splitting so as to create a parameter file for the hardware neural network. The present disclosure provides a novel neural network and a brain-like computing software and hardware system.

Abstract: A network-on-chip flit transmission method and a network-on-chip flit transmission apparatus. The method includes: receiving a current flit including an operation ID Op ID, an operation type Op Type, and a payload; when determining that acceleration processing needs to be performed on the current flit, determining, according to the Op Type, whether the payload of the current flit affects an execution result of a destination node of the current flit, where the execution result is a result obtained by executing, by the destination node, a task corresponding to the Op ID; and forwarding the current flit to a next node if a determining result is yes; and discarding the current flit if a determining result is no. Therefore, not only a quantity of flits that need to be transmitted on a network-on-chip can be greatly reduced, but also a calculation amount of the destination node can be reduced.

Abstract: A data processing method based on a multi-core processor chip, an apparatus, and a system are provided. The data processing method includes: obtaining, by a first processor core, a data processing task, where the data processing task includes a processing operation identifier and a storage address of to-be-processed data (202); determining, by the first processor core, a second processor core, where the second processor core corresponds to the storage address of the to-be-processed data (204); and sending, by the first processor core, the processing operation identifier and the storage address of the to-be-processed data to the second processor core (206). The data processing method is applied to a multi-core processor chip and improves working efficiency of the multi-core processor chip.

Abstract: A network-on-chip flit transmission method and a network-on-chip flit transmission apparatus. The method includes: receiving a current flit including an operation ID Op ID, an operation type Op Type, and a payload; when determining that acceleration processing needs to be performed on the current flit, determining, according to the Op Type, whether the payload of the current flit affects an execution result of a destination node of the current flit, where the execution result is a result obtained by executing, by the destination node, a task corresponding to the Op ID; and forwarding the current flit to a next node if a determining result is yes; and discarding the current flit if a determining result is no. Therefore, not only a quantity of flits that need to be transmitted on a network-on-chip can be greatly reduced, but also a calculation amount of the destination node can be reduced.