Patents by Inventor Youichi Gotoh
Youichi Gotoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140136581Abstract: In an example of the invention, a first storage subsystem includes a first router, a first processor, and a second processor. The first router receives a first write command and first write data for the first write command from a host. The first router transfers the first write command and the first write data to the second storage subsystem. Upon determination that a first processor cannot process the first write command because of a failure, the first router transfers the first write command to a second processor. The second processor performs processing to store the first write data to a first volume in accordance with the first write command.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: HITACHI, LTD.Inventors: Yasuhiko Yamaguchi, Kazuki Hongo, Youichi Gotoh
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Patent number: 8713266Abstract: A storage apparatus having a plurality of logical volumes includes a storage device, and a storage controller that operates each of the logical volumes as a virtual volume. A primary volume and a secondary volume are configured as a copy pair in which data in the primary volume can be copied to the secondary volume. If the primary volume receives a discard request for a unit physical storage area, the storage controller determines whether or not a unit physical storage area exists configuring the secondary volume corresponding to the unit physical storage area, which is a target of the discard request. If the unit physical storage area configuring the secondary volume exists, an instruction is transmitted to the secondary volume to discard the page or unit physical storage area assigned to the secondary volume.Type: GrantFiled: April 15, 2010Date of Patent: April 29, 2014Assignee: Hitachi, Ltd.Inventors: Michio Suetsugu, Hiroshi Abei, Haruaki Watanabe, Youichi Gotoh
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Patent number: 8694741Abstract: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from the received commands. Then, the adapter executes the extracted commands of the first kind with high priority within a given unit time until a given number of guaranteed activations is reached. At the same time, commands of a second kind are enqueued in a queue of commands. After the commands of the first kind are executed as many as the number of guaranteed activations, the commands of the second kind are executed in the unit time.Type: GrantFiled: August 2, 2012Date of Patent: April 8, 2014Assignee: Hitachi, Ltd.Inventors: Yasuhiko Yamaguchi, Youichi Gotoh
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Publication number: 20130246650Abstract: A computer system and frame transfer bandwidth optimization method capable of data transfer bandwidth control on a logical unit basis and according to the relevant storage tier in a storage apparatus are suggested. When encapsulating a first frame, in which transfer target data is stored, in a second frame and sending or receiving it between first and second nodes, the number of frames, that is, the number of a multiplicity of first frames to be stored in one second frame, is determined in advance for each storage tier or logical unit defined within a storage apparatus; and the multiplicity of first frames as many as the number of frames that is set in advance to a logical unit, which is a write destination or read destination of the relevant data, or a storage tier to which the relevant logical unit belongs, are stored in the second frame and sent to the other end of a communication link.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Applicant: HITACHI, LTD.Inventors: Masanao Tsuboki, Takashi Chikusa, Hiroshi Kuwabara, Youichi Gotoh
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Publication number: 20120297155Abstract: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from the received commands. Then, the adapter executes the extracted commands of the first kind with high priority within a given unit time until a given number of guaranteed activations is reached. At the same time, commands of a second kind are enqueued in a queue of commands. After the commands of the first kind are executed as many as the number of guaranteed activations, the commands of the second kind are executed in the unit time.Type: ApplicationFiled: August 2, 2012Publication date: November 22, 2012Applicant: Hitachi, Ltd.Inventors: Yasuhiko YAMAGUCHI, Youichi GOTOH
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Patent number: 8271749Abstract: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from the received commands. Then, the adapter executes the extracted commands of the first kind with high priority within a given unit time until a given number of guaranteed activations is reached. At the same time, commands of a second kind are enqueued in a queue of commands. After the commands of the first kind are executed as many as the number of guaranteed activations, the commands of the second kind are executed in the unit time.Type: GrantFiled: September 12, 2008Date of Patent: September 18, 2012Assignee: Hitachi, Ltd.Inventors: Yasuhiko Yamaguchi, Youichi Gotoh
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Patent number: 8099551Abstract: Provided is a storage controller capable of improving the access performance to the storage device by preventing an I/O access request to the storage device from being concentrated on certain I/O processors among a plurality of I/O processor, and causing the plurality of I/O processors to issue the I/O access request in a well balanced manner. With this storage control system, a plurality of stripe units are formed by striping the logical volume into a stripe size of an arbitrary storage capacity, and information regarding which I/O processor among the plurality of I/O processors will output the I/O request to which stripe unit among the plurality of stripe units is stored as the control information in the memory.Type: GrantFiled: September 24, 2010Date of Patent: January 17, 2012Assignee: Hitachi, Ltd.Inventors: Naotaka Kobayashi, Kunihito Matsuki, Hiroshi Ogasawara, Youichi Gotoh
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Publication number: 20110258406Abstract: A storage apparatus having a plurality of logical volumes, each providing a data storage area to an external device, comprises a storage device providing a physical storage area, and a storage controller creating a plurality of unit physical storage areas from the storage device, operating each of the logical volumes as a virtual volume in which, in response to a data TO request from the external device, the unit physical storage area is added to each of the logical volumes, selecting any one of the logical volumes as a primary volume, selecting any one of the rest of the logical volumes as a secondary volume, the primary volume and the secondary volume being configured as a copy pair in which data in the primary volume can be copied to the secondary volume, in the case that the primary volume receives a discarding request for the unit physical storage area from the external device, determining whether or not the unit physical storage are exists, the unit physical storage area configuring the secondary volumeType: ApplicationFiled: April 15, 2010Publication date: October 20, 2011Applicant: HITACHI, LTD.Inventors: Michio Suetsugu, Hiroshi Abei, Haruaki Watanabe, Youichi Gotoh
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Patent number: 7979603Abstract: A storage system including a queue corresponding to each priority level of command and an activation order control part. A command received from a host is accumulated in the queue corresponding to the specified priority. The activation order control part decides the number of activation object commands to be activated among accumulated commands, based on the priority corresponding to the queue. The activation order control part decides the activation order of the activation object commands, based on a activation object command number decided for each queue, so that the average value of logical response time of the activation object command may be shorter at the higher priority. The activation object command is activated in accordance with the decided activation order.Type: GrantFiled: December 12, 2008Date of Patent: July 12, 2011Assignee: Hitachi, Ltd.Inventors: Yasuhiko Yamaguchi, Ken Tokoro, Youichi Gotoh
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Patent number: 7886114Abstract: When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I/O request using the data transferred to the buffer memory.Type: GrantFiled: June 26, 2008Date of Patent: February 8, 2011Assignee: Hitachi, Ltd.Inventor: Youichi Gotoh
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Publication number: 20110029732Abstract: Provided is a storage controller capable of improving the access performance to the storage device by preventing an I/O access request to the storage device from being concentrated on certain I/O processors among a plurality of I/O processor, and causing the plurality of I/O processors to issue the I/O access request in a well balanced manner. With this storage control system, a plurality of stripe units are formed by striping the logical volume into a stripe size of an arbitrary storage capacity, and information regarding which I/O processor among the plurality of I/O processors will output the I/O request to which stripe unit among the plurality of stripe units is stored as the control information in the memory.Type: ApplicationFiled: September 24, 2010Publication date: February 3, 2011Inventors: Naotaka Kobayashi, Kunihito Matsuki, Hiroshi Ogasawara, Youichi Gotoh
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Publication number: 20100100645Abstract: To provide a storage system that can control both the number of commands activated per unit time and the response time of each command activated in accordance with the priority level of command. The storage system comprises a queue corresponding to each priority of command and an activation order control part. A command that the storage system receives from a host computer is accumulated in the queue corresponding to the priority specified from the command. The activation order control part decides, for each queue, the number of activation object commands that are the commands to be activated among a plurality of commands accumulated in the queue, based on the priority corresponding to the queue. And the activation order control part decides the activation order of the activation object commands, based on the activation object command number decided for each queue, so that the average value of logical response time of the activation object command may be shorter at the higher priority.Type: ApplicationFiled: December 12, 2008Publication date: April 22, 2010Inventors: Yasuhiko YAMAGUCHI, Ken Tokoro, Youichi Gotoh
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Publication number: 20100023712Abstract: A storage subsystem capable of processing time-critical control commands while suppressing deterioration of the system performance to a minimum. When various commands are received in a multiplex manner via the same port from plural host devices, the channel adapter of the storage subsystem extracts commands of a first kind from the received commands. Then, the adapter executes the extracted commands of the first kind with high priority within a given unit time until a given number of guaranteed activations is reached. At the same time, commands of a second kind are enqueued in a queue of commands. After the commands of the first kind are executed as many as the number of guaranteed activations, the commands of the second kind are executed in the unit time.Type: ApplicationFiled: September 12, 2008Publication date: January 28, 2010Inventors: Yasuhiko Yamaguchi, Youichi Gotoh
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Patent number: 7571289Abstract: The present invention allows a reserved state that prevails for an LDEV as a result of a host undergoing a system shutdown or the like to be confirmed and cancelled easily. The server 1 reserves the LDEV 4 and uses same exclusively. When the server 1 undergoes a system shutdown due to a fault or similar (S1), the LDEV 4 then remains reserved (S2). The server 2 is therefore unable to access the LDEV 4. The system administrator reads exclusive control information 6 in the memory 5 via the management terminal 7, and is thus able to display the reserved states of respective LDEVs on a terminal screen and confirm these states. The user then issues an instruction to cancel a reserved state from the management terminal 7 (S3). The disk array device 3 receives the cancellation instruction, and then cancels the reserved state by partially rewriting the exclusive control information 6.Type: GrantFiled: June 14, 2004Date of Patent: August 4, 2009Assignee: Hitachi, Ltd.Inventors: Youichi Gotoh, Takeshi Ido, Katsuhiro Uchiumi
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Patent number: 7478231Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.Type: GrantFiled: September 21, 2004Date of Patent: January 13, 2009Assignees: Hitachi, Ltd., Hitachi Software Engineering Co., Ltd.Inventors: Takeshi Ido, Youichi Gotoh, Shizuo Yokohata, Shigeo Honma, Toshiyuki Yoshino
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Publication number: 20080270689Abstract: When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I/O request using the data transferred to the buffer memory.Type: ApplicationFiled: June 26, 2008Publication date: October 30, 2008Inventor: Youichi Gotoh
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Patent number: 7421553Abstract: Under a hetero-environment in which different sorts of disk-systems are mixed with each other, a data guaranteeing operation can be carried out. When a cache controller of a local disk system receives a data writing request from a host computer, the cache controller stores data into a local disk provided in a disk device group. The data received from the host computer is also transmitted to a remote disk system and is stored in a remote disk. The data stored in the remote disk is immediately read, and the data written in the remote disk is compared with the data written in the local disk. As a result, since a data guarantee operation on the remote side is processed by the local disk system instead of the remote disk system, a data guaranteeing operation when a remote copying operation is performed can be carried out even in the storage system under a hetero-environment.Type: GrantFiled: September 15, 2006Date of Patent: September 2, 2008Assignee: Hitachi, Ltd.Inventors: Shinichi Nakayama, Youichi Gotoh, Keishi Tamura
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Patent number: 7337281Abstract: A channel adapter connected to a host has a local cache memory. The channel adapter duplexes and writes the write-data in the local cache memory in response to a data-write request from the host. Then, the channel adapter sends the write-completion to the host and transfers all of the write-data within the local cache memory to the main cache memory in asynchronous timing. The channel adapter manages directory information of the data within the local cache memory. In response to a data-read request from the host, the channel adapter checks whether the read-data hits or not in the local cache memory based on the directory information. If the read-data hits, the read-data is transferred from the local cache memory to the host.Type: GrantFiled: February 3, 2004Date of Patent: February 26, 2008Assignee: Hitachi, Ltd.Inventors: Yonggen Jin, Youichi Gotoh, Shinichi Nakayama
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Publication number: 20070168610Abstract: Provided is a storage controller capable of improving the access performance to the storage device by preventing an I/O access request to the storage device from being concentrated on certain I/O processors among a plurality of I/O processor, and causing the plurality of I/O processors to issue the I/O access request in a well balanced manner. With this storage control system, a plurality of stripe units are formed by striping the logical volume into a stripe size of an arbitrary storage capacity, and information regarding which I/O processor among the plurality of I/O processors will output the I/O request to which stripe unit among the plurality of stripe units is stored as the control information in the memory.Type: ApplicationFiled: March 15, 2006Publication date: July 19, 2007Inventors: Naotaka Kobayshi, Kunihito Matsuki, Hiroshi Ogasawara, Youichi Gotoh
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Publication number: 20070061518Abstract: When a first channel processor from among a plurality of channel processors receives an I/O request from a host system, a second channel processor, which is to execute a part of the processing to respond to the I/O request, is selected from among the channel processors based on the LM directories of the respective channel processors. The selected second channel processor checks whether there is a cache hit. If there is a cache hit, it transfers the data from the cache memory to the buffer memory. The first channel processor then processes the I/O request using the data transferred to the buffer memory.Type: ApplicationFiled: November 4, 2005Publication date: March 15, 2007Inventor: Youichi Gotoh