Abstract: A semiconductor integrated circuit for driving an LCD. The circuit has a shift register circuit portion (3) and a driver circuit portion (7). All the stages of the shift register circuit portion are formed adjacently to the outer fringe of a chip (30). All the stages of the driver circuit portion are formed along the central line (L1) of the chip. Signal electrodes (81-8n) for individual bits are formed in a belt-like region (33) extending in the X-direction along the central line (L1) and adjacently to the driver circuit portion. Output electrodes are arranged in a zigzag fashion. Since the output electrodes overlap with each other in the Y-direction, the width of the chip can be suppressed. Power supply voltages (VH, V0, V2, V3, V5) are applied to the driver circuit portion (7) through leads (36-40). These leads are connected so as to form a closed loop making one revolution around the output electrodes (81-8N) located in the center of the chip.

Abstract: A semiconductor integrated circuit for driving an LCD. The circuit has a shift register circuit portion (3) and a driver circuit portion (7). All the stages of the shift register circuit portion are formed adjacently to the outer fringe of a chip (30). All the stages of the driver circuit portion are formed along the central line (L1) of the chip. Signal electrodes (81-8N) for individual bits are formed in a belt-like region (33) extending in the X-direction along the central line (L1) and adjacently to the driver circuit portion. Output electrodes are arranged in a zigzag fashion. Since the output electrodes overlap with each other in the Y-direction, the width of the chip can be suppressed. Power supply voltages ( VH, V0, V2, V3, V5) are applied to the driver circuit portion (7) through leads (36-40). These leads are connected so as to form a closed loop making one revolution around the output electrodes (81-8N) located in the center of the chip.

Abstract: Signal management control units 47.sub.1 -47.sub.n of respective scan drivers LSI in an LCD module are cascade-connected and each have the same construction. A detected signal of the signal management control unit 47J is a data signal latch clock LP applied to a terminal CKB.sub.1. A detected signal of the signal management control unit 47.sub.2 is a frame start signal SP applied to a terminal CKB.sub.2. A detected signal of the signal management control unit 47n is an AC-transforming clock FR applied to a terminal CKBn. The signal management control unit 47.sub.1 includes a signal stop detection circuit 48 serving as a signal detection means for detecting a stop of the detected signal and a sequence processing circuit 51 consisting of a signal delay circuit 49 and a logic circuit 50. When stopping oscillations of, e. g., the frame start signal SP, outputs T.sub.1 -T.sub.n of the circuit 51 change to an L level. Hence, a display-off signal DF of the LCD module assumes the L level.

Abstract: A semiconductor integrated circuit for driving an LCD. The circuit has a shift register circuit portion (3) and a driver circuit portion (7). All the stages of the shift register circuit portion are formed adjacently to the outer fringe of a chip (30). All the stages of the driver circuit portion are formed along the central line (L.sub.1) of the chip. Signal electrodes (8.sub.1 -8.sub.N) for individual bits are formed in a belt-like region (33) extending in the X-direction along the central line (L.sub.1) and adjacently to the driver circuit portion. Output electrodes are arranged in a zigzag fashion. Since the output electrodes overlap with each other in the Y-direction, the width of the chip can be suppressed. Power supply voltages (V.sub.H, V.sub.0, V.sub.2, V.sub.3, V.sub.5) are applied to the driver circuit portion (7) through leads (36-40). These leads are connected so as to form a closed loop making one revolution around the output electrodes (8.sub.1 -8.sub.N) located in the center of the chip.

Abstract: Signal management control units 47.sub.1 -47.sub.n of respective scan drivers LSI in an LCD module are cascade-connected and each have the same construction. A detected signal of the signal management control unit 47I is a data signal latch clock LP applied to a terminal CKB.sub.1. A detected signal of the signal management control unit 47.sub.2 is a frame start signal SP applied to a terminal CKB.sub.2. A detected signal of the signal management control unit 47n is an AC-transforming clock FR applied to a terminal CKBn. The signal management control unit 47.sub.1 includes a signal stop detection circuit 48 serving as a signal detection means for detecting a stop of the detected signal and a sequence processing circuit 51 consisting of a signal delay circuit 49 and a logic circuit 50. When stopping oscillations of, e.g., the frame start signal SP, outputs T.sub.1 -T.sub.n of the circuit 51 change to an L level. Hence, a display-off signal DF of the LCD module assumes the L level.

Abstract: According to the rolling method and the apparatus to be used for its execution of the invention, by rolling a tube to be rolled by using four rolls possessing roll grooves for forming a caliber in a shape of having a relief portion, cold reducing or cold stretch reducing is done continuously without causing wall thickness deviation, and by sizing the rolled tube material by a die disposed at the exit side, the dimensional precision and yield of rolled tubes may be enhanced by a small number of stands.

Abstract: A digital display electronic stop-watch control circuit for facilitating the control of the start, stop, lap and reset functions in an electronic stop-watch is provided. The control circuit is provided for use in an electronic timepiece having counter circuitry for producing elapsed time signals, memory circuitry for storing said elapsed time signals and display circuitry for displaying either elapsed time or stored time in response to the elapsed time signals produced by the counter circuitry or in response to the stored time signals produced by the memory circuitry being respectively applied thereto. The control circuit of the instant invention is characterized by being coupled to the counter circuitry, memory circuitry and digital display circuitry. First and second manually operated switching circuits are respectively coupled to the control circuit.

Abstract: Signal management control units 471-47n of respective scan drivers LSI in an LCD module are cascade-connected and each have the same construction. A detected signal of the signal management control unit 47J is a data signal latch clock LP applied to a terminal CKB1. A detected signal of the signal management control unit 472 is a frame start signal SP applied to a terminal CKB2. A detected signal of the signal management control unit 47n is an AC-transforming clock FR applied to a terminal CKBn. The signal management control unit 471 includes a signal stop detection circuit 48 serving as a signal detection means for detecting a stop of the detected signal and a sequence processing circuit 51 consisting of a signal delay circuit 49 and a logic circuit 50. When stopping oscillations of, e. g., the frame start signal SP, outputs T1-Tn of the circuit 51 change to an L level. Hence, a display-off signal DF of the LCD module assumes the L level. A liquid crystal panel is forcibly set in a display-off mode.

Abstract: Signal management control units 471-47n of respective scan drivers LSI in an LCD module are cascade-connected and each have the same construction. A detected signal of the signal management control unit 47J is a data signal latch clock LP applied to a terminal CKB1. A detected signal of the signal management control unit 472 is a frame start signal SP applied to a terminal CKB2. A detected signal of the signal management control unit 47n is an AC-transforming clock FR applied to a terminal CKBn. The signal management control unit 471 includes a signal stop detection circuit 48 serving as a signal detection means for detecting a stop of the detected signal delay circuit 49 processing circuit 51 consisting of a signal delay circuit 49 and a logic circuit 50. When stopping oscillations of, e.g., the frame start signal SP, outputs T1-Tn of the circuit 51 change to an L level. Hence, a display-off signal DF of the LCD module assumes the L level. A liquid crystal panel is forcibly set in a display-off mode.